diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
index ca64fc47be..32060c79cb 100644
--- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -487,6 +487,7 @@ class WithTraceIOPunchthrough extends OverrideLazyIOBinder({
       val cfg = SpikeCosimConfig(
         isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
         priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""),
+        maxpglevels = tiles.headOption.map(_.tileParams.core.pgLevels).getOrElse(0),
         mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
         mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),
         pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0),
diff --git a/generators/testchipip b/generators/testchipip
index 0bd83bcf0b..541864d602 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 0bd83bcf0b9b82259e1e510ed755f1787c3458bc
+Subproject commit 541864d602ba9021e0256d7bf0da2a2a25acdb91