feat: first commit

Author: ttboma

.commitlintrc

@@ -0,0 +1,3 @@
+{
+    extends: ["@commitlint/config-conventional"]
+}

.gitignore

@@ -320,11 +320,13 @@ target/
 lib_managed/
 src_managed/
 project/boot/
+project/project
 project/plugins/project/
 
 # Scala-IDE specific
 .scala_dependencies
 .worksheet
+.bloop
 ### Java template
 *.class
 
@@ -339,3 +341,31 @@ project/plugins/project/
 # virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
 hs_err_pid*
 
+
+# Metals
+.metals
+project/metals.sbt
+
+# Eclipse
+bin/
+.classpath
+.project
+.settings
+.cache-main
+
+#User
+/*.vhd
+/*.v
+*.cf
+*.json
+*.vcd
+!tester/src/test/resources/*.vhd
+
+gen/
+simWorkspace/
+tmp/
+null
+
+book
+.DS_Store
+.DS_St

.mill-version

@@ -0,0 +1,23 @@
+repos:
+  - repo: https://github.com/pre-commit/pre-commit-hooks
+    rev: v4.6.0
+    hooks:
+      - id: trailing-whitespace
+      - id: end-of-file-fixer
+      - id: check-yaml
+      - id: check-toml
+      - id: check-added-large-files
+  - repo: https://github.com/alessandrojcm/commitlint-pre-commit-hook
+    rev: v9.16.0
+    hooks:
+      - id: commitlint
+        stages: [commit-msg]
+        additional_dependencies: ['@commitlint/config-conventional']
+  - repo: local
+    hooks:
+      - id: scalafmt
+        name: Run Scalafmt
+        description: Formats Scala code using Scalafmt
+        entry: scalafmt
+        language: system
+        types: [scala]

.pre-commit-config.yaml

@@ -0,0 +1,2 @@
+version = "3.7.15"
+runner.dialect = scala213

.scalafmt.conf

@@ -1,110 +1,7 @@
-Chisel Project Template
-=======================
+# Introduction
 
-You've done the [Chisel Bootcamp](https://github.com/freechipsproject/chisel-bootcamp), and now you
-are ready to start your own Chisel project.  The following procedure should get you started
-with a clean running [Chisel3](https://www.chisel-lang.org/) project.
+This is a demo project using [Chisel](https://github.com/chipsalliance/chisel). It begins with the [Chisel template](https://github.com/chipsalliance/chisel-template) and includes additional **pre-commit** configuration.
 
-## Make your own Chisel3 project
+I have included several practice solutions in the `src/main/scala/hdlbits` folder. The generated simulation files and Verilog files will be placed in the `gen` and `simWorkspace` folders.
 
-### Dependencies
-
-#### JDK 8 or newer
-
-We recommend LTS releases Java 8 and Java 11. You can install the JDK as your operating system recommends, or use the prebuilt binaries from [AdoptOpenJDK](https://adoptopenjdk.net/).
-
-#### SBT or mill
-
-SBT is the most common build tool in the Scala community. You can download it [here](https://www.scala-sbt.org/download.html).  
-mill is another Scala/Java build tool without obscure DSL like SBT. You can download it [here](https://github.com/com-lihaoyi/mill/releases)
-
-#### Verilator
-
-The test with `svsim` needs Verilator installed.
-See Verilator installation instructions [here](https://verilator.org/guide/latest/install.html).
-
-### How to get started
-
-#### Create a repository from the template
-
-This repository is a Github template. You can create your own repository from it by clicking the green `Use this template` in the top right.
-Please leave `Include all branches` **unchecked**; checking it will pollute the history of your new repository.
-For more information, see ["Creating a repository from a template"](https://docs.github.com/en/free-pro-team@latest/github/creating-cloning-and-archiving-repositories/creating-a-repository-from-a-template).
-
-#### Wait for the template cleanup workflow to complete
-
-After using the template to create your own blank project, please wait a minute or two for the `Template cleanup` workflow to run which will removes some template-specific stuff from the repository (like the LICENSE).
-Refresh the repository page in your browser until you see a 2nd commit by `actions-user` titled `Template cleanup`.
-
-
-#### Clone your repository
-
-Once you have created a repository from this template and the `Template cleanup` workflow has completed, you can click the green button to get a link for cloning your repository.
-Note that it is easiest to push to a repository if you set up SSH with Github, please see the [related documentation](https://docs.github.com/en/free-pro-team@latest/github/authenticating-to-github/connecting-to-github-with-ssh). SSH is required for pushing to a Github repository when using two-factor authentication.
-
-```sh
-git clone git@github.com:ttboma/chisel-hdlbits.git
-cd chisel-hdlbits
-```
-
-#### Set project organization and name in build.sbt
-
-The cleanup workflow will have attempted to provide sensible defaults for `ThisBuild / organization` and `name` in the `build.sbt`.
-Feel free to use your text editor of choice to change them as you see fit.
-
-#### Clean up the README.md file
-
-Again, use you editor of choice to make the README specific to your project.
-
-#### Add a LICENSE file
-
-It is important to have a LICENSE for open source (or closed source) code.
-This template repository has the Unlicense in order to allow users to add any license they want to derivative code.
-The Unlicense is stripped when creating a repository from this template so that users do not accidentally unlicense their own work.
-
-For more information about a license, check out the [Github Docs](https://docs.github.com/en/free-pro-team@latest/github/building-a-strong-community/adding-a-license-to-a-repository).
-
-#### Commit your changes
-```sh
-git commit -m 'Starting chisel-hdlbits'
-git push origin main
-```
-
-### Did it work?
-
-You should now have a working Chisel3 project.
-
-You can run the included test with:
-```sh
-sbt test
-```
-
-Alternatively, if you use Mill:
-```sh
-mill chisel-hdlbits.test
-```
-
-You should see a whole bunch of output that ends with something like the following lines
-```
-[info] Tests: succeeded 1, failed 0, canceled 0, ignored 0, pending 0
-[info] All tests passed.
-[success] Total time: 5 s, completed Dec 16, 2020 12:18:44 PM
-```
-If you see the above then...
-
-### It worked!
-
-You are ready to go. We have a few recommended practices and things to do.
-
-* Use packages and following conventions for [structure](https://www.scala-sbt.org/1.x/docs/Directories.html) and [naming](http://docs.scala-lang.org/style/naming-conventions.html)
-* Package names should be clearly reflected in the testing hierarchy
-* Build tests for all your work
-* Read more about testing in SBT in the [SBT docs](https://www.scala-sbt.org/1.x/docs/Testing.html)
-* This template includes a [test dependency](https://www.scala-sbt.org/1.x/docs/Library-Dependencies.html#Per-configuration+dependencies) on [ScalaTest](https://www.scalatest.org/). This, coupled with `svsim` (included with Chisel) and `verilator`, are a starting point for testing Chisel generators.
-  * You can remove this dependency in the build.sbt file if you want to
-* Change the name of your project in the build.sbt file
-* Change your README.md
-
-## Problems? Questions?
-
-Check out the [Chisel Users Community](https://www.chisel-lang.org/community.html) page for links to get in contact!
+Please note that these solutions are not necessarily optimal, but rather intended to help you gradually work through the SpinalHDL language.

README.md

@@ -6,22 +6,20 @@ import chisel3._
 // _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
 import _root_.circt.stage.ChiselStage
 
-/**
-  * Compute GCD using subtraction method.
-  * Subtracts the smaller from the larger until register y is zero.
-  * value in register x is then the GCD
+/** Compute GCD using subtraction method. Subtracts the smaller from the larger
+  * until register y is zero. value in register x is then the GCD
   */
 class GCD extends Module {
   val io = IO(new Bundle {
-    val value1        = Input(UInt(16.W))
-    val value2        = Input(UInt(16.W))
+    val value1 = Input(UInt(16.W))
+    val value2 = Input(UInt(16.W))
     val loadingValues = Input(Bool())
-    val outputGCD     = Output(UInt(16.W))
-    val outputValid   = Output(Bool())
+    val outputGCD = Output(UInt(16.W))
+    val outputValid = Output(Bool())
   })
 
-  val x  = Reg(UInt())
-  val y  = Reg(UInt())
+  val x = Reg(UInt())
+  val y = Reg(UInt())
 
   when(x > y) { x := x - y }
     .otherwise { y := y - x }
@@ -35,12 +33,12 @@ class GCD extends Module {
   io.outputValid := y === 0.U
 }
 
-/**
- * Generate Verilog sources and save it in file GCD.v
- */
+/** Generate Verilog sources and save it in file GCD.v
+  */
 object GCD extends App {
   ChiselStage.emitSystemVerilogFile(
     new GCD,
-    firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
+    firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info"),
+    args = Array("--target-dir", "gen/gcd")
   )
 }

build.sc

@@ -0,0 +1,34 @@
+package hdlbits.verilog_language
+
+import chisel3._
+
+// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
+import _root_.circt.stage.ChiselStage
+
+// https://hdlbits.01xz.net/wiki/7458
+case class HdlBits7458() extends Module {
+  val p1a = IO(Input(Bool()))
+  val p1b = IO(Input(Bool()))
+  val p1c = IO(Input(Bool()))
+  val p1d = IO(Input(Bool()))
+  val p1e = IO(Input(Bool()))
+  val p1f = IO(Input(Bool()))
+  val p1y = IO(Output(Bool()))
+  val p2a = IO(Input(Bool()))
+  val p2b = IO(Input(Bool()))
+  val p2c = IO(Input(Bool()))
+  val p2d = IO(Input(Bool()))
+  val p2y = IO(Output(Bool()))
+
+  p1y := (p1a & p1c & p1b) | (p1f & p1e & p1d)
+  p2y := (p2a & p2b) | (p2c & p2d)
+}
+
+// Generate Verilog sources and save it in file HdlBits7458.sv
+object HdlBits7458 extends App {
+  ChiselStage.emitSystemVerilogFile(
+    HdlBits7458(),
+    firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info"),
+    args = Array("--target-dir", "gen/hdlbits/verilog_language")
+  )
+}