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atrivedi-tsavoritesiAshish Trivedi
atrivedi-tsavoritesi
and
Ashish Trivedi
authored
FIR-595: Update configs to add modules required for virtualization and ethernet port (non functional for dummy interface) (#13)
* @FIR-595: Reducded the lower UDMA reserved area to only 256 MB * @FIR-595: Enabled nttables and iptables * @FIR-592: Moved the 128 MB reserved area to 0x60000000 * @FIR-595: Enable VXLAN and Wireguard * @FIR-595: Reverted the dtsi file * @FIR-595: Removed duplicate configs * @FIR-595: Added VXLAN and UDP Tunnel support to dumy interfaces * @FIR-595: Added debug prints * @FIR-595: Adding change to bring up eth0 * @FIR-595: Reverted changes to udp_tunnel_nic.c and dummy.c * @FIR-595: Addressed review comments and minimized diffs for eth0 --------- Co-authored-by: Ashish Trivedi <atrivedi@fpga2.tsavoritesi.net>
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‎arch/arm64/boot/dts/intel/fm87_ftile_10g_2port_ptp.dtsi

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright(C) 2022, Intel Corporation
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*/
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/* Add this piece of dtsi fragment as #include "fm87_ftile_25g_ptp.dtsi"
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* in the file socfpga_fm87_ftile_25g_ptp.dts. Compile it in the kernel along with
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* socfpga_agilex.dtsi
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*/
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/{
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soc {
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agilex_hps_bridges: bus@88000000 {
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compatible = "simple-bus";
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reg = <0x80000000 0x60000000>,
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<0xf9000000 0x00100000>;
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reg-names = "axi_h2f", "axi_h2f_lw";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>,
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<0x00000001 0x00000000 0x80000000 0x00040000>,
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<0x00000001 0x04040050 0x84040050 0x00000010>,
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<0x00000001 0x04040040 0x84040040 0x00000010>;
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qsfp_eth0: qsfp-eth0 {
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compatible = "sff,qsfp";
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i2c-bus = <&i2c0>;
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qsfpdd_initmode-gpio = <&qsfpdd_ctrl_pio 1 GPIO_ACTIVE_HIGH>;
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qsfpdd_modseln-gpio = <&qsfpdd_ctrl_pio 2 GPIO_ACTIVE_LOW>;
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qsfpdd_modprsn-gpio = <&qsfpdd_status_pio 0 GPIO_ACTIVE_LOW>;
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qsfpdd_resetn-gpio = <&qsfpdd_ctrl_pio 0 GPIO_ACTIVE_HIGH>;
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qsfpdd_intn-gpio = <&qsfpdd_status_pio 1 GPIO_ACTIVE_LOW>;
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agilex_hps_spim = <&qsfpdd_ctrl_pio 3 GPIO_ACTIVE_HIGH>;
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maximum-power-milliwatt = <1000>;
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status = "disable";
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/* status = "okay"; */
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};
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qsfpdd_status_pio: gpio@4040050 {
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compatible = "altr,pio-1.0";
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reg = <0x00000001 0x04040050 0x10>;
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interrupt-parent = <&intc>;
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interrupts = <0 22 4>;
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altr,gpio-bank-width = <4>;
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altr,interrupt-type = <2>;
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altr,interrupt_type = <2>;
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#gpio-cells = <2>;
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gpio-controller;
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status = "okay";
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/*status = "disable";*/
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};
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qsfpdd_ctrl_pio: gpio@4040040 {
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compatible = "altr,pio-1.0";
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reg = <0x00000001 0x04040040 0x10>;
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interrupt-parent = <&intc>;
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interrupts = <0 23 4>;
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altr,gpio-bank-width = <4>;
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altr,interrupt-type = <2>;
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altr,interrupt_type = <2>;
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#gpio-cells = <2>;
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gpio-controller;
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status = "okay";
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/*status = "disable"; */
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};
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};
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clocks {
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tod_in_clock: tod_in_clock {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <156250000>;
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clock-output-names = "tod_in_clock";
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};
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};
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ptp_clockcleaner: ptp_clockcleaner {
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compatible = "intel, freq-steering-zl-i2c";
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dpll-name = "zl30733";
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interface = "i2c";
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bus-num = <1>;
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bus-address = <0x70>;
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};
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tod_0_clk: tod_0_clk {
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compatible = "intel, tod";
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reg-names = "tod_ctrl",
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"pps_ctrl";
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reg = <0x84040000 0x00000040>,
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<0x84040100 0x00000040>;
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interrupt-parent = <&intc>;
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interrupt-names = "pps_irq";
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interrupts = <0 19 4>;
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clocks = <&tod_in_clock>;
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clock-names = "tod_clock";
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status = "okay";
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altr,has-ptp-clockcleaner;
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clock-cleaner = <&ptp_clockcleaner>;
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};
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hssiss_0_hssiss: hssiss_0_hssiss {
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compatible = "intel, hssiss-1.0";
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reg-names = "sscsr";
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reg = <0x88000000 0x04000000>;
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reset-mode ="reg";
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};
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hssi_0_eth: hssi_0_eth@88000000 {
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reg-names = "tx_pref" ,
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"tx_csr" ,
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"tx_fifo" ,
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"rx_pref" ,
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"rx_csr" ,
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"rx_fifo" ;
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reg = <0x8c480000 0x00000020>,
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<0x8c480020 0x00000020>,
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<0x8c480040 0x00000020>,
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<0x8c480080 0x00000020>,
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<0x8c4800A0 0x00000020>,
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<0x8c4800C0 0x00000010>;
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compatible = "altr,hssi-ftile-1.0";
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tile_chan = <0x8>;
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hssi_port = <0x8>;
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phy-mode = "10gbase-r";
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tod = <&tod_0_clk>;
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hssiss = <&hssiss_0_hssiss>;
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pma_type = <0x0>; // FGT - 0x00, FHT = 0x1000
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altr,tx-pma-delay-ns = <0xD>;
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altr,rx-pma-delay-ns = <0x8>;
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altr,tx-pma-delay-fns = <0x24D>;
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altr,rx-pma-delay-fns = <0x3E97>;
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altr,tx-external-phy-delay-ns = <0x0>;
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altr,rx-external-phy-delay-ns = <0x0>;
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fec-cw-pos-rx = <0x0>;
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fec-type="no-fec";
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interrupt-parent = <&intc>;
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interrupt-names = "tx_irq", "rx_irq";
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interrupts = <0 24 4>, <0 25 4>;
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qsfp-lane = <0x0>;
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rx-fifo-depth = <0x4000>;
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tx-fifo-depth = <0x1000>;
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rx-fifo-almost-full = <0x2000>;
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rx-fifo-almost-empty = <0x1000>;
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altr,has-ptp;
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ptp_accu_mode = "Advanced";
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ptp_tx_routing_adj = <0xDE9F>; //56,991
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ptp_rx_routing_adj = <0xD625>; //54,821
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status = "okay";
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fixed-link {
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speed =<10000>;
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full-duplex;
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};
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};
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hssi_1_eth: hssi_1_eth@88000000 {
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reg-names = "tx_pref" ,
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"tx_csr" ,
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"tx_fifo" ,
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"rx_pref" ,
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"rx_csr" ,
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"rx_fifo" ;
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reg = <0x8c4C0000 0x00000020>,
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<0x8c4C0020 0x00000020>,
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<0x8c4C0040 0x00000020>,
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<0x8c4C0080 0x00000020>,
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<0x8c4C00A0 0x00000020>,
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<0x8c4C00C0 0x00000010>;
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compatible = "altr,hssi-ftile-1.0";
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tile_chan = <0x9>;
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hssi_port = <0x9>;
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phy-mode = "10gbase-r";
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tod = <&tod_0_clk>;
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hssiss = <&hssiss_0_hssiss>;
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pma_type = <0x0>; // FGT - 0x00, FHT = 0x1000
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altr,tx-pma-delay-ns = <0xD>;
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altr,rx-pma-delay-ns = <0x8>;
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altr,tx-pma-delay-fns = <0x24D>;
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altr,rx-pma-delay-fns = <0x3E97>;
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altr,tx-external-phy-delay-ns = <0x0>;
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altr,rx-external-phy-delay-ns = <0x0>;
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fec-cw-pos-rx = <0x0>;
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fec-type="no-fec";
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interrupt-parent = <&intc>;
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interrupt-names = "tx_irq", "rx_irq";
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interrupts = <0 26 4>, <0 27 4>;
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qsfp-lane = <0x0>;
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rx-fifo-depth = <0x4000>;
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tx-fifo-depth = <0x1000>;
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rx-fifo-almost-full = <0x2000>;
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rx-fifo-almost-empty = <0x1000>;
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altr,has-ptp;
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ptp_accu_mode = "Advanced";
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ptp_tx_routing_adj = <0xDE3C>; //56,892
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ptp_rx_routing_adj = <0xD73F>; //55,103
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status = "okay";
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fixed-link {
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speed =<10000>;
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full-duplex;
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};
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};
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};
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};

‎arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts

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@@ -4,6 +4,8 @@
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*/
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#include "socfpga_agilex_bittware.dtsi"
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#include "socfpga_agilex_pcie_root_port.dtsi"
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#include "fm87_ftile_10g_2port_ptp.dtsi"
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/ {
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model = "SoCFPGA Agilex BittWare";
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};
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&gmac2 {
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status = "disabled";
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status = "okay";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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‎arch/arm64/configs/defconfig

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@@ -1606,3 +1606,60 @@ CONFIG_BLK_DEV_NVME=y
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#CONFIG_NVME_HWMON=y
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#CONFIG_NVME_FC=y
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CONFIG_DUMMY=m
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##########################################
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# For Flannel enable config flags
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# For NFT tables, STP, VXLAN and Wireguard
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#########################################
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CONFIG_CFS_BANDWIDTH=y
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CONFIG_NETFILTER_NETLINK=m
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CONFIG_NETFILTER_XT_MATCH_OWNER=m
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CONFIG_NET_SCH_HFSC=m
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CONFIG_NET_SCH_FQ_CODEL=m
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CONFIG_NET_UDP_TUNNEL=m
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CONFIG_NF_DUP_NETDEV=m
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CONFIG_NF_LOG_BRIDGE=m
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CONFIG_NF_TABLES_ARP=y
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CONFIG_NF_TABLES_BRIDGE=y
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CONFIG_NF_TABLES_INET=y
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CONFIG_NF_TABLES_IPV4=y
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CONFIG_NF_TABLES_IPV6=y
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CONFIG_NF_TABLES=m
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CONFIG_NF_TABLES_NETDEV=y
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CONFIG_NFT_BRIDGE_REJECT=m
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CONFIG_NFT_CHAIN_NAT_IPV4=m
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CONFIG_NFT_CHAIN_ROUTE_IPV4=m
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CONFIG_NFT_CHAIN_ROUTE_IPV6=m
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CONFIG_NFT_COMPAT=m
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CONFIG_NFT_COUNTER=m
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CONFIG_NFT_CT=m
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CONFIG_NFT_DUP_IPV4=m
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CONFIG_NFT_DUP_IPV6=m
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CONFIG_NFT_DUP_NETDEV=m
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CONFIG_NFT_FIB_INET=m
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CONFIG_NFT_FIB_IPV4=m
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CONFIG_NFT_FIB_IPV6=m
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CONFIG_NFT_FIB_NETDEV=m
1643+
CONFIG_NFT_FWD_NETDEV=m
1644+
CONFIG_NFT_HASH=m
1645+
CONFIG_NFT_LIMIT=m
1646+
CONFIG_NFT_LOG=m
1647+
CONFIG_NFT_MASQ_IPV4=m
1648+
CONFIG_NFT_MASQ=m
1649+
CONFIG_NFT_NAT=m
1650+
CONFIG_NFT_NUMGEN=m
1651+
CONFIG_NFT_QUEUE=m
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CONFIG_NFT_QUOTA=m
1653+
CONFIG_NFT_REDIR_IPV4=m
1654+
CONFIG_NFT_REDIR=m
1655+
CONFIG_NFT_REJECT=m
1656+
CONFIG_NFT_REJECT_INET=m
1657+
CONFIG_NFT_REJECT_IPV4=m
1658+
CONFIG_NFT_REJECT_IPV6=m
1659+
CONFIG_NFT_CONNLIMIT=m
1660+
CONFIG_NFT_TUNNEL=m
1661+
CONFIG_NFT_OBJREF=m
1662+
CONFIG_NFT_QUEUE=m
1663+
CONFIG_STP=m
1664+
CONFIG_VXLAN=m
1665+
CONFIG_WIREGUARD=m

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