pulp-platform / common_cells
Common SystemVerilog components
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Common SystemVerilog components
RISC-V Debug Support for our PULP RISC-V Cores
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
A minimal GPU design in Verilog to learn how GPUs work from the ground up
OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.