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[BITSTREAM SERVER] Bitstream server integration (apache#38)
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‎vta/NEWS.md‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,13 @@
1-
TVM Change Log
1+
VTA Change Log
22
==============
33

44
This file records the changes in VTA stack in reverse chronological order.
55

66

77
## Initial version
88

9-
- Vivado based hardware
10-
- Driver for PYNQ
9+
- Vivado based hardware.
10+
- Driver for PYNQ board.
1111
- Runtime library.
1212
- TVM compiler stack.
13+
- Resnet-18 example.

‎vta/apps/pynq_rpc/README.md‎

Lines changed: 1 addition & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -31,21 +31,10 @@ From there, clone the VTA repository:
3131
git clone git@github.com:uwsaml/vta.git --recursive
3232
```
3333

34-
Next, clone the TVM repository:
35-
```bash
36-
git clone git@github.com:dmlc/tvm.git --recursive
37-
```
38-
39-
TVM is rapidly changing, and to ensure stability, we keep track of working TVM checkpoints.
40-
As of now, the TVM checkpoint `e4c2af9abdcb3c7aabafba8084414d7739c17c4c` is known to work with VTA.
41-
```bash
42-
git checkout e4c2af9abdcb3c7aabafba8084414d7739c17c4c
43-
```
44-
4534
Now, ssh into your **Pynq board** to build the TVM runtime with the following commands:
4635
```bash
4736
ssh xilinx@192.168.2.99 # ssh if you haven't done so
48-
cd ~/tvm
37+
cd ~/vta/nnvm/tvm
4938
cp make/config.mk .
5039
echo USE_RPC=1 >> config.mk
5140
make runtime -j2
@@ -57,7 +46,6 @@ We're now ready to build the Pynq RPC server on the Pynq board.
5746
```bash
5847
ssh xilinx@192.168.2.99 # ssh if you haven't done so
5948
cd ~/vta
60-
export TVM_PATH = /home/xilinx/tvm
6149
make
6250
```
6351

‎vta/examples/resnet18/pynq/README.md‎

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@ In order to run this example you'll need to have:
44
* VTA installed
55
* TVM installed
66
* NNVM installed
7+
* MxNet installed
78
* A Pynq-based RPC server running
89

910
## VTA installation
@@ -26,9 +27,9 @@ git clone git@github.com:dmlc/tvm.git --recursive
2627
```
2728

2829
TVM is rapidly changing, and to ensure stability, we keep track of working TVM checkpoints.
29-
As of now, the TVM checkpoint `e4c2af9abdcb3c7aabafba8084414d7739c17c4c` is known to work with VTA.
30+
As of now, the TVM checkpoint `168f099155106d1188dbc54ac00acc02900a3c6f` is known to work with VTA.
3031
```bash
31-
git checkout e4c2af9abdcb3c7aabafba8084414d7739c17c4c
32+
git checkout 168f099155106d1188dbc54ac00acc02900a3c6f
3233
```
3334

3435
Before building TVM, copy the `make/config.mk` file into the root TVM directory:
@@ -59,7 +60,7 @@ Clone the NNVM repository from `tqchen` in the directory of your choosing:
5960
git clone git@github.com:tqchen/nnvm.git --recursive
6061
```
6162

62-
To run this example, we rely on a special branch of NNVM: `qt`:
63+
To run this example, we rely on a special branch of NNVM until these changes get merged back into the main repo: `qt`:
6364
```bash
6465
cd <nnvm root>
6566
git checkout qt
@@ -76,6 +77,10 @@ Finally update your `~/.bashrc` file to include the NNVM python libraries in you
7677
export PYTHONPATH=<nnvm root>/python:${PYTHONPATH}
7778
```
7879

80+
## MxNet Installation
81+
82+
Follow the [MxNet Installation Instructions](https://mxnet.incubator.apache.org)
83+
7984
## Pynq RPC Server Setup
8085
8186
Follow the [Pynq RPC Server Guide](https://github.com/uwsaml/vta/tree/master/apps/pynq_rpc/README.md)

‎vta/examples/resnet18/pynq/imagenet_predict.py‎

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -15,8 +15,6 @@
1515

1616
bfactor = 1
1717
cfactor = 16
18-
host = "pynq"
19-
port = 9091
2018
verbose = False
2119
# only run fpga component, mark non-conv ops as nop
2220
debug_fpga_only = False
@@ -27,8 +25,7 @@
2725
CATEG_FILE = 'synset.txt'
2826
RESNET_GRAPH_FILE = 'quantize_graph.json'
2927
RESNET_PARAMS_FILE = 'quantize_params.pkl'
30-
BITSTREAM_FILE = 'vta.bit'
31-
for file in [TEST_FILE, CATEG_FILE, RESNET_GRAPH_FILE, RESNET_PARAMS_FILE, BITSTREAM_FILE]:
28+
for file in [TEST_FILE, CATEG_FILE, RESNET_GRAPH_FILE, RESNET_PARAMS_FILE]:
3229
if not os.path.isfile(file):
3330
print ("Downloading {}".format(file))
3431
wget.download(url+file)
@@ -43,7 +40,6 @@
4340
if vta.get_env().TARGET == "sim":
4441
target_host = "llvm"
4542

46-
4743
synset = eval(open(os.path.join(CATEG_FILE)).read())
4844
image = Image.open(os.path.join(TEST_FILE)).resize((224, 224))
4945

@@ -138,8 +134,17 @@ def mark_nop(graph, conv_layer=-1, skip_conv_layer=()):
138134
remote = rpc.LocalSession()
139135
print("local session")
140136
else:
137+
host = os.environ.get("VTA_PYNQ_RPC_HOST", None)
138+
assert host
139+
port = os.environ.get("VTA_PYNQ_RPC_PORT", "9091")
140+
port = int(port)
141141
remote = rpc.connect(host, port)
142142

143+
# Program FPGA, and build runtime if necessary
144+
# Overwrite bitstream with a path to your own if you built it yourself
145+
vta.reconfig_runtime(remote)
146+
vta.program_fpga(remote, bitstream=None)
147+
143148
remote.upload(temp.relpath("graphlib.o"))
144149
lib = remote.load_module("graphlib.o")
145150
ctx = remote.ext_dev(0) if target.device_name == "vta" else remote.cpu(0)

‎vta/hardware/xilinx/Makefile‎

Lines changed: 9 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -45,26 +45,21 @@ VTA_WGT_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-wgtbuffsize)
4545
VTA_ACC_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-accbuffsize)
4646
VTA_OUT_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-outbuffsize)
4747

48+
#---------------------
49+
# FPGA Parameters
50+
#--------------------
51+
VTA_CLOCK_FREQ = $(shell ${VTA_CONFIG} --get-fpgafreq)
52+
VTA_TARGET_PER = $(shell ${VTA_CONFIG} --get-fpgaper)
53+
4854
#---------------------
4955
# Compilation parameters
5056
#--------------------
5157

5258
# Number of threads during compilation
5359
VTA_HW_COMP_THREADS = 8
5460

55-
# Target Frequency
56-
VTA_HW_COMP_CLOCK_FREQ = 100
57-
58-
# Timing closure compensation (0 for none, 3 for highest)
59-
VTA_HW_COMP_TIMING_COMP = 0
60-
61-
# Derive clock target period
62-
TARGET_PER = \
63-
$(shell echo "$$(( (1000 + $(VTA_HW_COMP_CLOCK_FREQ) - 1) / $(VTA_HW_COMP_CLOCK_FREQ) - $(VTA_HW_COMP_TIMING_COMP)))" )
64-
6561
# Derive config name
66-
CONF_ROOT = $(shell ${VTA_CONFIG} --cfg-str)
67-
CONF = $(CONF_ROOT)_$(VTA_HW_COMP_CLOCK_FREQ)MHz_$(TARGET_PER)ns
62+
CONF = $(shell ${VTA_CONFIG} --cfg-str)
6863
IP_BUILD_PATH = $(BUILD_DIR)/hls/$(CONF)
6964
HW_BUILD_PATH = $(BUILD_DIR)/vivado/$(CONF)
7065

@@ -90,7 +85,7 @@ $(IP_PATH): $(SRC_DIR)/*
9085
cd $(IP_BUILD_PATH) && \
9186
$(VIVADO_HLS) -f $(SCRIPT_DIR)/hls.tcl \
9287
-tclargs $(SRC_DIR) $(SIM_DIR) $(TEST_DIR) $(INCLUDE_DIR) \
93-
$(MODE) $(DEBUG) $(NO_DSP) $(NO_ALU) $(TARGET_PER) \
88+
$(MODE) $(DEBUG) $(NO_DSP) $(NO_ALU) $(VTA_TARGET_PER) \
9489
$(VTA_INP_WIDTH) $(VTA_WGT_WIDTH) $(VTA_ACC_WIDTH) $(VTA_OUT_WIDTH) \
9590
$(VTA_BATCH) $(VTA_IN_BLOCK) $(VTA_OUT_BLOCK) \
9691
$(VTA_UOP_BUFF_SIZE) $(VTA_INP_BUFF_SIZE) $(VTA_WGT_BUFF_SIZE) \
@@ -104,7 +99,7 @@ $(BIT_PATH): $(IP_PATH)
10499
mkdir -p $(HW_BUILD_PATH)
105100
cd $(HW_BUILD_PATH) && \
106101
$(VIVADO) -mode tcl -source $(SCRIPT_DIR)/vivado.tcl \
107-
-tclargs $(BUILD_DIR)/hls/$(CONF) $(VTA_HW_COMP_THREADS) $(VTA_HW_COMP_CLOCK_FREQ) \
102+
-tclargs $(BUILD_DIR)/hls/$(CONF) $(VTA_HW_COMP_THREADS) $(VTA_CLOCK_FREQ) \
108103
$(VTA_INP_WIDTH) $(VTA_WGT_WIDTH) $(VTA_OUT_WIDTH) \
109104
$(VTA_BATCH) $(VTA_IN_BLOCK) $(VTA_OUT_BLOCK) \
110105
$(VTA_INP_BUFF_SIZE) $(VTA_WGT_BUFF_SIZE) $(VTA_OUT_BUFF_SIZE)

‎vta/hardware/xilinx/README.md‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,5 @@ make
6767

6868
The local `Makefile` containts several variables that can be tweaked by the user:
6969
* `VTA_HW_COMP_THREADS`: determines the number of threads used for the Vivado compilation job (default 8 threads).
70-
* `VTA_HW_COMP_CLOCK_FREQ`: determines the target frequency of the VTA design (default 100MHz). It can only be set to 100, 142, 167 or 200MHz.
71-
* `VTA_HW_COMP_TIMING_COMP`: determines how much additional slack must be provided to close timing (default 0ns). Generally when utilization is high for an FPGA design, setting this paramter to 1, 2 or 3 can help close timing.
7270

7371
Once the compilation completes, the generated bitstream can be found under `<vta root>/build/hardware/xilinx/vivado/<design name>/export/vta.bit`.

‎vta/make/config.json‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,16 @@
11
{
22
"TARGET" : "pynq",
3+
"HW_FREQ" : 100,
4+
"HW_CLK_TARGET" : 8,
5+
"HW_VER" : "0.0.0",
36
"LOG_INP_WIDTH" : 3,
47
"LOG_WGT_WIDTH" : 3,
58
"LOG_ACC_WIDTH" : 5,
69
"LOG_OUT_WIDTH" : 3,
710
"LOG_BATCH" : 0,
811
"LOG_BLOCK_IN" : 4,
912
"LOG_BLOCK_OUT" : 4,
10-
"LOG_UOP_BUFF_SIZE" : 14,
13+
"LOG_UOP_BUFF_SIZE" : 15,
1114
"LOG_INP_BUFF_SIZE" : 15,
1215
"LOG_WGT_BUFF_SIZE" : 18,
1316
"LOG_ACC_BUFF_SIZE" : 17

‎vta/make/sim_sample.json‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,16 @@
11
{
22
"TARGET" : "sim",
3+
"HW_FREQ" : 100,
4+
"HW_CLK_TARGET" : 8,
5+
"HW_VER" : "0.0.0",
36
"LOG_INP_WIDTH" : 3,
47
"LOG_WGT_WIDTH" : 3,
58
"LOG_ACC_WIDTH" : 5,
69
"LOG_OUT_WIDTH" : 3,
710
"LOG_BATCH" : 0,
811
"LOG_BLOCK_IN" : 4,
912
"LOG_BLOCK_OUT" : 4,
10-
"LOG_UOP_BUFF_SIZE" : 14,
13+
"LOG_UOP_BUFF_SIZE" : 15,
1114
"LOG_INP_BUFF_SIZE" : 15,
1215
"LOG_WGT_BUFF_SIZE" : 18,
1316
"LOG_ACC_BUFF_SIZE" : 17

‎vta/make/vta_config.py‎

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,10 @@ def main():
5454
help="returns log of accum buffer size in B")
5555
parser.add_argument("--get-outbuffsize", action="store_true",
5656
help="returns log of output buffer size in B")
57+
parser.add_argument("--get-fpgafreq", action="store_true",
58+
help="returns FPGA frequency")
59+
parser.add_argument("--get-fpgaper", action="store_true",
60+
help="returns HLS target clock period")
5761
args = parser.parse_args()
5862

5963
if len(sys.argv) == 1:
@@ -91,7 +95,8 @@ def main():
9195
print(pkg.cfg_json)
9296

9397
if args.cfg_str:
94-
cfg_str = "{}x{}x{}_{}bx{}b_{}_{}_{}_{}".format(
98+
# Needs to match the BITSTREAM string in python/vta/environment.py
99+
cfg_str = "{}x{}x{}_{}bx{}b_{}_{}_{}_{}_{}MHz_{}ns_v{}".format(
95100
(1 << cfg["LOG_BATCH"]),
96101
(1 << cfg["LOG_BLOCK_IN"]),
97102
(1 << cfg["LOG_BLOCK_OUT"]),
@@ -100,8 +105,11 @@ def main():
100105
cfg["LOG_UOP_BUFF_SIZE"],
101106
cfg["LOG_INP_BUFF_SIZE"],
102107
cfg["LOG_WGT_BUFF_SIZE"],
103-
cfg["LOG_ACC_BUFF_SIZE"])
104-
print cfg_str
108+
cfg["LOG_ACC_BUFF_SIZE"],
109+
cfg["HW_FREQ"],
110+
cfg["HW_CLK_TARGET"],
111+
cfg["HW_VER"].replace('.', '_'))
112+
print(cfg_str)
105113

106114
if args.get_inpwidth:
107115
print(cfg["LOG_INP_WIDTH"])
@@ -139,5 +147,11 @@ def main():
139147
if args.get_accbuffsize:
140148
print(cfg["LOG_ACC_BUFF_SIZE"])
141149

150+
if args.get_fpgafreq:
151+
print(cfg["HW_FREQ"])
152+
153+
if args.get_fpgaper:
154+
print(cfg["HW_CLK_TARGET"])
155+
142156
if __name__ == "__main__":
143157
main()

‎vta/python/vta/__init__.py‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,11 +8,10 @@
88

99
__version__ = "0.1.0"
1010

11-
11+
from .bitstream import get_bitstream_path, download_bitstream
1212
from .environment import get_env, Environment
1313
from .rpc_client import reconfig_runtime, program_fpga
1414

15-
1615
try:
1716
from . import top
1817
from .build_module import build_config, lower, build

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