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tmoreau89tqchen
tmoreau89
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tqchen
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[HARDWARE, TEST] Fixed hardware generation flow (apache#34)
1 parent 726e047 commit 08e4bd5

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14 files changed

+550
-198
lines changed

14 files changed

+550
-198
lines changed

‎apps/pynq_rpc/start_rpc_server.sh‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
#!/bin/bash
2-
export PYTHONPATH=${PYTHONPATH}:/home/xilinx/tvm/python:/home/xilinx/vta/python
2+
export PYTHONPATH=${PYTHONPATH}:/home/xilinx/vta/nnvm/tvm/python:/home/xilinx/vta/python
33
export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:/opt/python3.6/lib/python3.6/site-packages/pynq/drivers/
44
python -m vta.exec.rpc_server

‎hardware/xilinx/Makefile‎

Lines changed: 46 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -13,24 +13,37 @@ VIVADO_HLS = vivado_hls
1313
VIVADO = vivado
1414
HSI = hsi
1515

16-
# HLS Mode
17-
MODE = all
16+
# HLS mode
17+
MODE = skip_sim
18+
# Debug flag
19+
DEBUG = false
1820
# SLURM
1921
SLURM = false
2022
# Prevent generation of DSP
2123
NO_DSP = false
2224
# Prevent generation of ALU
2325
NO_ALU = false
2426

25-
# Include top-level config file
26-
ifndef config
27-
ifneq ("$(wildcard ../../config.mk)", "")
28-
config = ../../config.mk
29-
else
30-
config = ../../make/config.mk
31-
endif
32-
endif
33-
include $(config)
27+
# Process VTA JSON config
28+
VTA_CONFIG = python $(CURDIR)/../../make/vta_config.py
29+
CFLAGS := $(shell ${VTA_CONFIG} --cflags)
30+
VTA_TARGET := $(shell ${VTA_CONFIG} --target)
31+
32+
#---------------------
33+
# VTA Parameters
34+
#--------------------
35+
VTA_INP_WIDTH := $(shell ${VTA_CONFIG} --get-inpwidth)
36+
VTA_WGT_WIDTH := $(shell ${VTA_CONFIG} --get-wgtwidth)
37+
VTA_ACC_WIDTH := $(shell ${VTA_CONFIG} --get-accwidth)
38+
VTA_OUT_WIDTH := $(shell ${VTA_CONFIG} --get-outwidth)
39+
VTA_BATCH := $(shell ${VTA_CONFIG} --get-batch)
40+
VTA_IN_BLOCK := $(shell ${VTA_CONFIG} --get-blockin)
41+
VTA_OUT_BLOCK := $(shell ${VTA_CONFIG} --get-blockout)
42+
VTA_UOP_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-uopbuffsize)
43+
VTA_INP_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-inpbuffsize)
44+
VTA_WGT_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-wgtbuffsize)
45+
VTA_ACC_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-accbuffsize)
46+
VTA_OUT_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-outbuffsize)
3447

3548
#---------------------
3649
# Compilation parameters
@@ -50,8 +63,8 @@ TARGET_PER = \
5063
$(shell echo "$$(( (1000 + $(VTA_HW_COMP_CLOCK_FREQ) - 1) / $(VTA_HW_COMP_CLOCK_FREQ) - $(VTA_HW_COMP_TIMING_COMP)))" )
5164

5265
# Derive config name
53-
CONF = \
54-
$(VTA_BATCH)x$(VTA_IN_BLOCK)x$(VTA_OUT_BLOCK)_$(VTA_INP_WIDTH)bx$(VTA_WGT_WIDTH)b_$(VTA_LOG_UOP_BUFF_SIZE)_$(VTA_LOG_INP_BUFF_SIZE)_$(VTA_LOG_WGT_BUFF_SIZE)_$(VTA_LOG_ACC_BUFF_SIZE)_$(VTA_HW_COMP_CLOCK_FREQ)MHz_$(TARGET_PER)ns
66+
CONF_ROOT = $(shell ${VTA_CONFIG} --cfg-str)
67+
CONF = $(CONF_ROOT)_$(VTA_HW_COMP_CLOCK_FREQ)MHz_$(TARGET_PER)ns
5568
IP_BUILD_PATH = $(BUILD_DIR)/hls/$(CONF)
5669
HW_BUILD_PATH = $(BUILD_DIR)/vivado/$(CONF)
5770

@@ -60,26 +73,34 @@ ifeq ($(SLURM), true)
6073
HW_BUILD_PATH = /scratch/vivado/$(CONF)
6174
endif
6275

63-
.PHONY: all ip bit driver clean clean_all
76+
# IP file path
77+
IP_PATH = $(BUILD_DIR)/hls/$(CONF)/solution0/impl/ip/xilinx_com_hls_vta_1_0.zip
78+
79+
# Bitstream file path
80+
BIT_PATH = $(BUILD_DIR)/vivado/$(CONF)/export/$(CONF).bit
6481

65-
all: bit
82+
.PHONY: all ip bit bsp clean clean_all
6683

67-
ip:
84+
all: bsp
85+
ip: $(IP_PATH)
86+
bit: $(BIT_PATH)
87+
88+
$(IP_PATH): $(SRC_DIR)/*
6889
mkdir -p $(IP_BUILD_PATH)
6990
cd $(IP_BUILD_PATH) && \
7091
$(VIVADO_HLS) -f $(SCRIPT_DIR)/hls.tcl \
71-
-tclargs $(SRC_DIR) $(SIM_DIR) $(TEST_DIR) $(INCLUDE_DIR) $(TARGET_PER) \
72-
$(VTA_LOG_INP_WIDTH) $(VTA_LOG_WGT_WIDTH) $(VTA_LOG_ACC_WIDTH) $(VTA_LOG_OUT_WIDTH) \
73-
$(VTA_LOG_BATCH) $(VTA_LOG_BLOCK_OUT) $(VTA_LOG_BLOCK_IN) \
74-
$(VTA_LOG_UOP_BUFF_SIZE) $(VTA_LOG_INP_BUFF_SIZE) $(VTA_LOG_WGT_BUFF_SIZE) \
75-
$(VTA_LOG_ACC_BUFF_SIZE) $(VTA_LOG_OUT_BUFF_SIZE) \
76-
$(MODE) $(NO_DSP) $(NO_ALU)
92+
-tclargs $(SRC_DIR) $(SIM_DIR) $(TEST_DIR) $(INCLUDE_DIR) \
93+
$(MODE) $(DEBUG) $(NO_DSP) $(NO_ALU) $(TARGET_PER) \
94+
$(VTA_INP_WIDTH) $(VTA_WGT_WIDTH) $(VTA_ACC_WIDTH) $(VTA_OUT_WIDTH) \
95+
$(VTA_BATCH) $(VTA_IN_BLOCK) $(VTA_OUT_BLOCK) \
96+
$(VTA_UOP_BUFF_SIZE) $(VTA_INP_BUFF_SIZE) $(VTA_WGT_BUFF_SIZE) \
97+
$(VTA_ACC_BUFF_SIZE) $(VTA_OUT_BUFF_SIZE)
7798
ifeq ($(SLURM), true)
7899
mkdir -p $(BUILD_DIR)/hls
79100
mv $(IP_BUILD_PATH) $(BUILD_DIR)/hls/.
80101
endif
81102

82-
bit: ip
103+
$(BIT_PATH): $(IP_PATH)
83104
mkdir -p $(HW_BUILD_PATH)
84105
cd $(HW_BUILD_PATH) && \
85106
$(VIVADO) -mode tcl -source $(SCRIPT_DIR)/vivado.tcl \
@@ -92,12 +113,12 @@ ifeq ($(SLURM), true)
92113
mv $(HW_BUILD_PATH) $(BUILD_DIR)/vivado/.
93114
endif
94115

95-
driver: bit
116+
bsp: $(BIT_PATH)
96117
cd $(HW_BUILD_PATH) && $(HSI) -mode tcl -source $(SCRIPT_DIR)/hsi.tcl -nojournal -nolog
97118
cd $(HW_BUILD_PATH)/bsp && make
98119

99120
clean:
100121
rm -rf *.out *.log *.sb figures
101122

102-
clean_all: clean
123+
cleanall: clean
103124
rm -rf $(BUILD_DIR)

‎hardware/xilinx/scripts/hls.tcl‎

Lines changed: 45 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -9,65 +9,69 @@
99
# Arg 2: path to sim sources
1010
# Arg 3: path to test sources
1111
# Arg 4: path to include sources
12-
# Arg 5: target clock period
13-
# Arg 6: input type width (log)
14-
# Arg 7: weight type width (log)
15-
# Arg 8: accum type width (log)
16-
# Arg 9: output type width (log)
17-
# Arg 10: batch size (log)
18-
# Arg 11: in block size (log)
19-
# Arg 12: out block size (log)
20-
# Arg 13: uop buffer size in B (log)
21-
# Arg 14: inp buffer size in B (log)
22-
# Arg 15: wgt buffer size in B (log)
23-
# Arg 16: acc buffer size in B (log)
24-
# Arg 17: out buffer size in B (log)
25-
# Arg 18: mode
26-
# Arg 19: no_dsp
27-
# Arg 20: no_alu
12+
# Arg 5: mode
13+
# Arg 6: debug
14+
# Arg 7: no_dsp
15+
# Arg 8: no_alu
16+
# Arg 9: target clock period
17+
# Arg 10: input type width (log)
18+
# Arg 11: weight type width (log)
19+
# Arg 12: accum type width (log)
20+
# Arg 13: output type width (log)
21+
# Arg 14: batch size (log)
22+
# Arg 15: in block size (log)
23+
# Arg 16: out block size (log)
24+
# Arg 17: uop buffer size in B (log)
25+
# Arg 18: inp buffer size in B (log)
26+
# Arg 19: wgt buffer size in B (log)
27+
# Arg 20: acc buffer size in B (log)
28+
# Arg 21: out buffer size in B (log)
2829

29-
if { [llength $argv] eq 22 } {
30+
if { [llength $argv] eq 23 } {
3031
set src_dir [lindex $argv 2]
3132
set sim_dir [lindex $argv 3]
3233
set test_dir [lindex $argv 4]
3334
set include_dir [lindex $argv 5]
34-
set target_period [lindex $argv 6]
35-
set inp_width [lindex $argv 7]
36-
set wgt_width [lindex $argv 8]
37-
set acc_width [lindex $argv 9]
38-
set out_width [lindex $argv 10]
39-
set batch [lindex $argv 11]
40-
set block_in [lindex $argv 12]
41-
set block_out [lindex $argv 13]
42-
set uop_buff_size [lindex $argv 14]
43-
set inp_buff_size [lindex $argv 15]
44-
set wgt_buff_size [lindex $argv 16]
45-
set acc_buff_size [lindex $argv 17]
46-
set out_buff_size [lindex $argv 18]
47-
set mode [lindex $argv 19]
48-
set no_dsp [lindex $argv 20]
49-
set no_alu [lindex $argv 21]
35+
set mode [lindex $argv 6]
36+
set debug [lindex $argv 7]
37+
set no_dsp [lindex $argv 8]
38+
set no_alu [lindex $argv 9]
39+
set target_period [lindex $argv 10]
40+
set inp_width [lindex $argv 11]
41+
set wgt_width [lindex $argv 12]
42+
set acc_width [lindex $argv 13]
43+
set out_width [lindex $argv 14]
44+
set batch [lindex $argv 15]
45+
set block_in [lindex $argv 16]
46+
set block_out [lindex $argv 17]
47+
set uop_buff_size [lindex $argv 18]
48+
set inp_buff_size [lindex $argv 19]
49+
set wgt_buff_size [lindex $argv 20]
50+
set acc_buff_size [lindex $argv 21]
51+
set out_buff_size [lindex $argv 22]
5052
} else {
5153
set src_dir "../src"
5254
set sim_dir "../sim"
5355
set test_dir "../../src/test"
5456
set include_dir "../../include"
57+
set mode "all"
58+
set debug "false"
59+
set no_dsp "true"
60+
set no_alu "false"
5561
set target_period 10
5662
set inp_width 3
5763
set wgt_width 3
5864
set acc_width 5
5965
set out_width 3
6066
set batch 1
61-
set block_out 4
6267
set block_in 4
68+
set block_out 4
6369
set uop_buff_size 15
6470
set inp_buff_size 15
6571
set wgt_buff_size 15
6672
set acc_buff_size 17
6773
set out_buff_size 15
68-
set mode "all"
69-
set no_dsp "true"
70-
set no_alu "false"
74+
exit
7175
}
7276

7377
# Initializes the HLS design and sets HLS pragmas for memory partitioning.
@@ -124,12 +128,15 @@ proc init_design {per inp_width wgt_width out_width batch block_in block_out} {
124128

125129
# C define flags to pass to compiler
126130
set cflags "-I $include_dir -I $src_dir -I $test_dir \
127-
-DVTA_DEBUG=0 -DVTA_LOG_WGT_WIDTH=$wgt_width -DVTA_LOG_INP_WIDTH=$inp_width \
131+
-DVTA_LOG_WGT_WIDTH=$wgt_width -DVTA_LOG_INP_WIDTH=$inp_width \
128132
-DVTA_LOG_ACC_WIDTH=$acc_width -DVTA_LOG_OUT_WIDTH=$out_width \
129133
-DVTA_LOG_BATCH=$batch -DVTA_LOG_BLOCK_OUT=$block_out -DVTA_LOG_BLOCK_IN=$block_in \
130134
-DVTA_LOG_UOP_BUFF_SIZE=$uop_buff_size -DVTA_LOG_INP_BUFF_SIZE=$inp_buff_size \
131135
-DVTA_LOG_WGT_BUFF_SIZE=$wgt_buff_size -DVTA_LOG_ACC_BUFF_SIZE=$acc_buff_size \
132136
-DVTA_LOG_OUT_BUFF_SIZE=$out_buff_size"
137+
if {$debug=="true"} {
138+
append cflags " -DVTA_DEBUG=1"
139+
}
133140
if {$no_dsp=="true"} {
134141
append cflags " -DNO_DSP"
135142
}

‎hardware/xilinx/scripts/vivado.tcl‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -26,15 +26,15 @@ if { [llength $argv] eq 12 } {
2626
set ip_path [lindex $argv 0]
2727
set num_threads [lindex $argv 1]
2828
set clock_freq [lindex $argv 2]
29-
set inp_width [lindex $argv 3]
30-
set wgt_width [lindex $argv 4]
31-
set out_width [lindex $argv 5]
32-
set batch [lindex $argv 6]
33-
set out_block [lindex $argv 7]
34-
set in_block [lindex $argv 8]
35-
set inp_mem_size [lindex $argv 9]
36-
set wgt_mem_size [lindex $argv 10]
37-
set out_mem_size [lindex $argv 11]
29+
set inp_width [expr 1 << [lindex $argv 3]]
30+
set wgt_width [expr 1 << [lindex $argv 4]]
31+
set out_width [expr 1 << [lindex $argv 5]]
32+
set batch [expr 1 << [lindex $argv 6]]
33+
set out_block [expr 1 << [lindex $argv 7]]
34+
set in_block [expr 1 << [lindex $argv 8]]
35+
set inp_mem_size [expr 1 << [lindex $argv 9]]
36+
set wgt_mem_size [expr 1 << [lindex $argv 10]]
37+
set out_mem_size [expr 1 << [lindex $argv 11]]
3838
if {$clock_freq eq 100} {
3939
set clock_id 0
4040
puts "Setting clock frequency to 100MHz"

‎hardware/xilinx/sim/vta_test.cc‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,5 +53,8 @@ int main(void) {
5353
status |= blocked_gemm_test(256, 256, VTA_BLOCK_OUT*4, true, 1);
5454
status |= blocked_gemm_test(256, 256, VTA_BLOCK_OUT*4, false, 1);
5555

56+
// Simple GEMM unit test
57+
status |= gemm_test(64, 64, 64, true);
58+
5659
return status;
5760
}

‎make/config.json‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@
77
"LOG_BATCH" : 0,
88
"LOG_BLOCK_IN" : 4,
99
"LOG_BLOCK_OUT" : 4,
10-
"LOG_UOP_BUFF_SIZE" : 15,
10+
"LOG_UOP_BUFF_SIZE" : 14,
1111
"LOG_INP_BUFF_SIZE" : 15,
12-
"LOG_WGT_BUFF_SIZE" : 15,
12+
"LOG_WGT_BUFF_SIZE" : 18,
1313
"LOG_ACC_BUFF_SIZE" : 17
1414
}

‎make/sim_sample.json‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@
77
"LOG_BATCH" : 0,
88
"LOG_BLOCK_IN" : 4,
99
"LOG_BLOCK_OUT" : 4,
10-
"LOG_UOP_BUFF_SIZE" : 15,
10+
"LOG_UOP_BUFF_SIZE" : 14,
1111
"LOG_INP_BUFF_SIZE" : 15,
12-
"LOG_WGT_BUFF_SIZE" : 15,
12+
"LOG_WGT_BUFF_SIZE" : 18,
1313
"LOG_ACC_BUFF_SIZE" : 17
1414
}

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