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hauke
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ralfbaechle
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phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module
This driver starts the DWC2 core(s) built into the XWAY SoCs and provides the PHY interfaces for each core. The phy instances can be passed to the dwc2 driver, which already supports the generic phy interface. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Rob Herring <robh@kernel.org> Cc: martin.blumenstingl@googlemail.com Cc: john@phrozen.org Cc: andy.shevchenko@gmail.com Cc: p.zabel@pengutronix.de Cc: mark.rutland@arm.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Cc: linux-watchdog@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-spi@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17127/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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‎Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt‎

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@@ -0,0 +1,40 @@
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Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
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===========================================
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This binding describes the USB PHY hardware provided by the RCU module on the
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Lantiq XWAY SoCs.
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This node has to be a sub node of the Lantiq RCU block.
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-------------------------------------------------------------------------------
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Required properties (controller (parent) node):
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- compatible : Should be one of
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"lantiq,ase-usb2-phy"
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"lantiq,danube-usb2-phy"
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"lantiq,xrx100-usb2-phy"
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"lantiq,xrx200-usb2-phy"
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"lantiq,xrx300-usb2-phy"
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- reg : Defines the following sets of registers in the parent
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syscon device
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- Offset of the USB PHY configuration register
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- Offset of the USB Analog configuration
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register (only for xrx200 and xrx200)
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- clocks : References to the (PMU) "phy" clk gate.
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- clock-names : Must be "phy"
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- resets : References to the RCU USB configuration reset bits.
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- reset-names : Must be one of the following:
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"phy" (optional)
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"ctrl" (shared)
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-------------------------------------------------------------------------------
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Example for the USB PHYs on an xRX200 SoC:
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usb_phy0: usb2-phy@18 {
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compatible = "lantiq,xrx200-usb2-phy";
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reg = <0x18 4>, <0x38 4>;
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clocks = <&pmu PMU_GATE_USB0_PHY>;
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clock-names = "phy";
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resets = <&reset1 4 4>, <&reset0 4 4>;
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reset-names = "phy", "ctrl";
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#phy-cells = <0>;
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};

‎arch/mips/lantiq/xway/sysctrl.c‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -469,8 +469,8 @@ void __init ltq_soc_init(void)
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470470
if (of_machine_is_compatible("lantiq,grx390") ||
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of_machine_is_compatible("lantiq,ar10")) {
472-
clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
473-
clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
472+
clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P);
473+
clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P);
474474
/* rc 0 */
475475
clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
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clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -490,8 +490,8 @@ void __init ltq_soc_init(void)
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else
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clkdev_add_static(CLOCK_133M, CLOCK_133M,
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CLOCK_133M, CLOCK_133M);
493-
clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
494-
clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
493+
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
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clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
495495
clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
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clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
497497
clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
@@ -500,8 +500,8 @@ void __init ltq_soc_init(void)
500500
} else if (of_machine_is_compatible("lantiq,grx390")) {
501501
clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
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ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
503-
clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
504-
clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
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clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
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clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
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/* rc 2 */
506506
clkdev_add_pmu("1a800000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P);
507507
clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
@@ -513,8 +513,8 @@ void __init ltq_soc_init(void)
513513
} else if (of_machine_is_compatible("lantiq,ar10")) {
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clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(),
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ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
516-
clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
517-
clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
516+
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
517+
clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
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clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |
519519
PMU_PPE_DP | PMU_PPE_TC);
520520
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
@@ -526,10 +526,10 @@ void __init ltq_soc_init(void)
526526
} else if (of_machine_is_compatible("lantiq,vr9")) {
527527
clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
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ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
529-
clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
530-
clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
531-
clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
532-
clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
529+
clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
530+
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
531+
clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
532+
clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
533533
clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
534534
clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
535535
clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -550,10 +550,10 @@ void __init ltq_soc_init(void)
550550
} else if (of_machine_is_compatible("lantiq,ar9")) {
551551
clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
552552
ltq_ar9_fpi_hz(), CLOCK_250M);
553-
clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
554-
clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
555-
clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
556-
clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
553+
clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
554+
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
555+
clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
556+
clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
557557
clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
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clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
559559
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
@@ -562,8 +562,8 @@ void __init ltq_soc_init(void)
562562
} else {
563563
clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
564564
ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
565-
clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
566-
clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
565+
clkdev_add_pmu("1f203018.usb2-phy", "ctrl", 1, 0, PMU_USB0);
566+
clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
567567
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
568568
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
569569
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);

‎drivers/phy/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -52,6 +52,7 @@ source "drivers/phy/allwinner/Kconfig"
5252
source "drivers/phy/amlogic/Kconfig"
5353
source "drivers/phy/broadcom/Kconfig"
5454
source "drivers/phy/hisilicon/Kconfig"
55+
source "drivers/phy/lantiq/Kconfig"
5556
source "drivers/phy/marvell/Kconfig"
5657
source "drivers/phy/motorola/Kconfig"
5758
source "drivers/phy/qualcomm/Kconfig"

‎drivers/phy/Makefile‎

Lines changed: 1 addition & 1 deletion
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@@ -7,9 +7,9 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
77
obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o
88
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
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obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
10-
1110
obj-$(CONFIG_ARCH_SUNXI) += allwinner/
1211
obj-$(CONFIG_ARCH_MESON) += amlogic/
12+
obj-$(CONFIG_LANTIQ) += lantiq/
1313
obj-$(CONFIG_ARCH_RENESAS) += renesas/
1414
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
1515
obj-$(CONFIG_ARCH_TEGRA) += tegra/

‎drivers/phy/lantiq/Kconfig‎

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@@ -0,0 +1,9 @@
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#
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# Phy drivers for Lantiq / Intel platforms
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#
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config PHY_LANTIQ_RCU_USB2
5+
tristate "Lantiq XWAY SoC RCU based USB PHY"
6+
depends on OF && (SOC_TYPE_XWAY || COMPILE_TEST)
7+
select GENERIC_PHY
8+
help
9+
Support for the USB PHY(s) on the Lantiq / Intel XWAY family SoCs.

‎drivers/phy/lantiq/Makefile‎

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@@ -0,0 +1 @@
1+
obj-$(CONFIG_PHY_LANTIQ_RCU_USB2) += phy-lantiq-rcu-usb2.o

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