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drm/tegra: dc: Support more formats
Also, split up formats into per-SoC lists because not all generations support all of them. Note that the list is now exhaustive for all RGB formats, but not for YUV and indexed formats. Signed-off-by: Thierry Reding <treding@nvidia.com>
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-22
lines changed

4 files changed

+235
-22
lines changed

‎drivers/gpu/drm/tegra/dc.c‎

Lines changed: 137 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -298,12 +298,60 @@ static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
298298
spin_unlock_irqrestore(&dc->lock, flags);
299299
}
300300

301-
static const u32 tegra_primary_plane_formats[] = {
302-
DRM_FORMAT_XBGR8888,
301+
static const u32 tegra20_primary_formats[] = {
302+
DRM_FORMAT_ARGB4444,
303+
DRM_FORMAT_ARGB1555,
304+
DRM_FORMAT_RGB565,
305+
DRM_FORMAT_RGBA5551,
303306
DRM_FORMAT_ABGR8888,
304-
DRM_FORMAT_XRGB8888,
305307
DRM_FORMAT_ARGB8888,
308+
};
309+
310+
static const u32 tegra114_primary_formats[] = {
311+
DRM_FORMAT_ARGB4444,
312+
DRM_FORMAT_ARGB1555,
313+
DRM_FORMAT_RGB565,
314+
DRM_FORMAT_RGBA5551,
315+
DRM_FORMAT_ABGR8888,
316+
DRM_FORMAT_ARGB8888,
317+
/* new on Tegra114 */
318+
DRM_FORMAT_ABGR4444,
319+
DRM_FORMAT_ABGR1555,
320+
DRM_FORMAT_BGRA5551,
321+
DRM_FORMAT_XRGB1555,
322+
DRM_FORMAT_RGBX5551,
323+
DRM_FORMAT_XBGR1555,
324+
DRM_FORMAT_BGRX5551,
325+
DRM_FORMAT_BGR565,
326+
DRM_FORMAT_BGRA8888,
327+
DRM_FORMAT_RGBA8888,
328+
DRM_FORMAT_XRGB8888,
329+
DRM_FORMAT_XBGR8888,
330+
};
331+
332+
static const u32 tegra124_primary_formats[] = {
333+
DRM_FORMAT_ARGB4444,
334+
DRM_FORMAT_ARGB1555,
306335
DRM_FORMAT_RGB565,
336+
DRM_FORMAT_RGBA5551,
337+
DRM_FORMAT_ABGR8888,
338+
DRM_FORMAT_ARGB8888,
339+
/* new on Tegra114 */
340+
DRM_FORMAT_ABGR4444,
341+
DRM_FORMAT_ABGR1555,
342+
DRM_FORMAT_BGRA5551,
343+
DRM_FORMAT_XRGB1555,
344+
DRM_FORMAT_RGBX5551,
345+
DRM_FORMAT_XBGR1555,
346+
DRM_FORMAT_BGRX5551,
347+
DRM_FORMAT_BGR565,
348+
DRM_FORMAT_BGRA8888,
349+
DRM_FORMAT_RGBA8888,
350+
DRM_FORMAT_XRGB8888,
351+
DRM_FORMAT_XBGR8888,
352+
/* new on Tegra124 */
353+
DRM_FORMAT_RGBX8888,
354+
DRM_FORMAT_BGRX8888,
307355
};
308356

309357
static int tegra_plane_atomic_check(struct drm_plane *plane,
@@ -461,8 +509,8 @@ static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
461509
if (!plane)
462510
return ERR_PTR(-ENOMEM);
463511

464-
num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
465-
formats = tegra_primary_plane_formats;
512+
num_formats = dc->soc->num_primary_formats;
513+
formats = dc->soc->primary_formats;
466514

467515
/*
468516
* XXX compute offset so that we can directly access windows.
@@ -643,12 +691,71 @@ static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
643691
return &plane->base;
644692
}
645693

646-
static const uint32_t tegra_overlay_plane_formats[] = {
647-
DRM_FORMAT_XBGR8888,
694+
static const u32 tegra20_overlay_formats[] = {
695+
DRM_FORMAT_ARGB4444,
696+
DRM_FORMAT_ARGB1555,
697+
DRM_FORMAT_RGB565,
698+
DRM_FORMAT_RGBA5551,
699+
DRM_FORMAT_ABGR8888,
700+
DRM_FORMAT_ARGB8888,
701+
/* planar formats */
702+
DRM_FORMAT_UYVY,
703+
DRM_FORMAT_YUYV,
704+
DRM_FORMAT_YUV420,
705+
DRM_FORMAT_YUV422,
706+
};
707+
708+
static const u32 tegra114_overlay_formats[] = {
709+
DRM_FORMAT_ARGB4444,
710+
DRM_FORMAT_ARGB1555,
711+
DRM_FORMAT_RGB565,
712+
DRM_FORMAT_RGBA5551,
648713
DRM_FORMAT_ABGR8888,
649-
DRM_FORMAT_XRGB8888,
650714
DRM_FORMAT_ARGB8888,
715+
/* new on Tegra114 */
716+
DRM_FORMAT_ABGR4444,
717+
DRM_FORMAT_ABGR1555,
718+
DRM_FORMAT_BGRA5551,
719+
DRM_FORMAT_XRGB1555,
720+
DRM_FORMAT_RGBX5551,
721+
DRM_FORMAT_XBGR1555,
722+
DRM_FORMAT_BGRX5551,
723+
DRM_FORMAT_BGR565,
724+
DRM_FORMAT_BGRA8888,
725+
DRM_FORMAT_RGBA8888,
726+
DRM_FORMAT_XRGB8888,
727+
DRM_FORMAT_XBGR8888,
728+
/* planar formats */
729+
DRM_FORMAT_UYVY,
730+
DRM_FORMAT_YUYV,
731+
DRM_FORMAT_YUV420,
732+
DRM_FORMAT_YUV422,
733+
};
734+
735+
static const u32 tegra124_overlay_formats[] = {
736+
DRM_FORMAT_ARGB4444,
737+
DRM_FORMAT_ARGB1555,
651738
DRM_FORMAT_RGB565,
739+
DRM_FORMAT_RGBA5551,
740+
DRM_FORMAT_ABGR8888,
741+
DRM_FORMAT_ARGB8888,
742+
/* new on Tegra114 */
743+
DRM_FORMAT_ABGR4444,
744+
DRM_FORMAT_ABGR1555,
745+
DRM_FORMAT_BGRA5551,
746+
DRM_FORMAT_XRGB1555,
747+
DRM_FORMAT_RGBX5551,
748+
DRM_FORMAT_XBGR1555,
749+
DRM_FORMAT_BGRX5551,
750+
DRM_FORMAT_BGR565,
751+
DRM_FORMAT_BGRA8888,
752+
DRM_FORMAT_RGBA8888,
753+
DRM_FORMAT_XRGB8888,
754+
DRM_FORMAT_XBGR8888,
755+
/* new on Tegra124 */
756+
DRM_FORMAT_RGBX8888,
757+
DRM_FORMAT_BGRX8888,
758+
/* planar formats */
652759
DRM_FORMAT_UYVY,
653760
DRM_FORMAT_YUYV,
654761
DRM_FORMAT_YUV420,
@@ -673,8 +780,8 @@ static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
673780
plane->index = index;
674781
plane->depth = 0;
675782

676-
num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
677-
formats = tegra_overlay_plane_formats;
783+
num_formats = dc->soc->num_overlay_formats;
784+
formats = dc->soc->overlay_formats;
678785

679786
err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
680787
&tegra_plane_funcs, formats,
@@ -1730,6 +1837,10 @@ static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
17301837
.has_powergate = false,
17311838
.broken_reset = true,
17321839
.has_nvdisplay = false,
1840+
.num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
1841+
.primary_formats = tegra20_primary_formats,
1842+
.num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
1843+
.overlay_formats = tegra20_overlay_formats,
17331844
};
17341845

17351846
static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
@@ -1741,6 +1852,10 @@ static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
17411852
.has_powergate = false,
17421853
.broken_reset = false,
17431854
.has_nvdisplay = false,
1855+
.num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
1856+
.primary_formats = tegra20_primary_formats,
1857+
.num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
1858+
.overlay_formats = tegra20_overlay_formats,
17441859
};
17451860

17461861
static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
@@ -1752,6 +1867,10 @@ static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
17521867
.has_powergate = true,
17531868
.broken_reset = false,
17541869
.has_nvdisplay = false,
1870+
.num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
1871+
.primary_formats = tegra114_primary_formats,
1872+
.num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
1873+
.overlay_formats = tegra114_overlay_formats,
17551874
};
17561875

17571876
static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
@@ -1763,6 +1882,10 @@ static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
17631882
.has_powergate = true,
17641883
.broken_reset = false,
17651884
.has_nvdisplay = false,
1885+
.num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
1886+
.primary_formats = tegra114_primary_formats,
1887+
.num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
1888+
.overlay_formats = tegra114_overlay_formats,
17661889
};
17671890

17681891
static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
@@ -1774,6 +1897,10 @@ static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
17741897
.has_powergate = true,
17751898
.broken_reset = false,
17761899
.has_nvdisplay = false,
1900+
.num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
1901+
.primary_formats = tegra114_primary_formats,
1902+
.num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
1903+
.overlay_formats = tegra114_overlay_formats,
17771904
};
17781905

17791906
static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {

‎drivers/gpu/drm/tegra/dc.h‎

Lines changed: 18 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,10 @@ struct tegra_dc_soc_info {
6161
bool has_nvdisplay;
6262
const struct tegra_windowgroup_soc *wgrps;
6363
unsigned int num_wgrps;
64+
const u32 *primary_formats;
65+
unsigned int num_primary_formats;
66+
const u32 *overlay_formats;
67+
unsigned int num_overlay_formats;
6468
};
6569

6670
struct tegra_dc {
@@ -582,9 +586,9 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
582586
#define WIN_COLOR_DEPTH_P4 2
583587
#define WIN_COLOR_DEPTH_P8 3
584588
#define WIN_COLOR_DEPTH_B4G4R4A4 4
585-
#define WIN_COLOR_DEPTH_B5G5R5A 5
589+
#define WIN_COLOR_DEPTH_B5G5R5A1 5
586590
#define WIN_COLOR_DEPTH_B5G6R5 6
587-
#define WIN_COLOR_DEPTH_AB5G5R5 7
591+
#define WIN_COLOR_DEPTH_A1B5G5R5 7
588592
#define WIN_COLOR_DEPTH_B8G8R8A8 12
589593
#define WIN_COLOR_DEPTH_R8G8B8A8 13
590594
#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
@@ -599,8 +603,20 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
599603
#define WIN_COLOR_DEPTH_YUV422R 23
600604
#define WIN_COLOR_DEPTH_YCbCr422RA 24
601605
#define WIN_COLOR_DEPTH_YUV422RA 25
606+
#define WIN_COLOR_DEPTH_R4G4B4A4 27
607+
#define WIN_COLOR_DEPTH_R5G5B5A 28
608+
#define WIN_COLOR_DEPTH_AR5G5B5 29
609+
#define WIN_COLOR_DEPTH_B5G5R5X1 30
610+
#define WIN_COLOR_DEPTH_X1B5G5R5 31
611+
#define WIN_COLOR_DEPTH_R5G5B5X1 32
612+
#define WIN_COLOR_DEPTH_X1R5G5B5 33
613+
#define WIN_COLOR_DEPTH_R5G6B5 34
614+
#define WIN_COLOR_DEPTH_A8R8G8B8 35
615+
#define WIN_COLOR_DEPTH_A8B8G8R8 36
602616
#define WIN_COLOR_DEPTH_B8G8R8X8 37
603617
#define WIN_COLOR_DEPTH_R8G8B8X8 38
618+
#define WIN_COLOR_DEPTH_X8B8G8R8 65
619+
#define WIN_COLOR_DEPTH_X8R8G8B8 66
604620

605621
#define DC_WIN_POSITION 0x704
606622
#define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */

‎drivers/gpu/drm/tegra/hub.c‎

Lines changed: 20 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,9 +26,27 @@
2626
#include "plane.h"
2727

2828
static const u32 tegra_shared_plane_formats[] = {
29-
DRM_FORMAT_XBGR8888,
30-
DRM_FORMAT_XRGB8888,
29+
DRM_FORMAT_ARGB1555,
3130
DRM_FORMAT_RGB565,
31+
DRM_FORMAT_RGBA5551,
32+
DRM_FORMAT_ARGB8888,
33+
DRM_FORMAT_ABGR8888,
34+
/* new on Tegra114 */
35+
DRM_FORMAT_ABGR4444,
36+
DRM_FORMAT_ABGR1555,
37+
DRM_FORMAT_BGRA5551,
38+
DRM_FORMAT_XRGB1555,
39+
DRM_FORMAT_RGBX5551,
40+
DRM_FORMAT_XBGR1555,
41+
DRM_FORMAT_BGRX5551,
42+
DRM_FORMAT_BGR565,
43+
DRM_FORMAT_XRGB8888,
44+
DRM_FORMAT_XBGR8888,
45+
/* planar formats */
46+
DRM_FORMAT_UYVY,
47+
DRM_FORMAT_YUYV,
48+
DRM_FORMAT_YUV420,
49+
DRM_FORMAT_YUV422,
3250
};
3351

3452
static inline unsigned int tegra_plane_offset(struct tegra_shared_plane *plane,

‎drivers/gpu/drm/tegra/plane.c‎

Lines changed: 60 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -110,24 +110,76 @@ int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap)
110110
*swap = BYTE_SWAP_NOSWAP;
111111

112112
switch (fourcc) {
113-
case DRM_FORMAT_XBGR8888:
114-
*format = WIN_COLOR_DEPTH_R8G8B8X8;
113+
case DRM_FORMAT_ARGB4444:
114+
*format = WIN_COLOR_DEPTH_B4G4R4A4;
115115
break;
116116

117-
case DRM_FORMAT_ABGR8888:
118-
*format = WIN_COLOR_DEPTH_R8G8B8A8;
117+
case DRM_FORMAT_ARGB1555:
118+
*format = WIN_COLOR_DEPTH_B5G5R5A1;
119119
break;
120120

121-
case DRM_FORMAT_XRGB8888:
122-
*format = WIN_COLOR_DEPTH_B8G8R8X8;
121+
case DRM_FORMAT_RGB565:
122+
*format = WIN_COLOR_DEPTH_B5G6R5;
123+
break;
124+
125+
case DRM_FORMAT_RGBA5551:
126+
*format = WIN_COLOR_DEPTH_A1B5G5R5;
123127
break;
124128

125129
case DRM_FORMAT_ARGB8888:
126130
*format = WIN_COLOR_DEPTH_B8G8R8A8;
127131
break;
128132

129-
case DRM_FORMAT_RGB565:
130-
*format = WIN_COLOR_DEPTH_B5G6R5;
133+
case DRM_FORMAT_ABGR8888:
134+
*format = WIN_COLOR_DEPTH_R8G8B8A8;
135+
break;
136+
137+
case DRM_FORMAT_ABGR4444:
138+
*format = WIN_COLOR_DEPTH_R4G4B4A4;
139+
break;
140+
141+
case DRM_FORMAT_ABGR1555:
142+
*format = WIN_COLOR_DEPTH_R5G5B5A;
143+
break;
144+
145+
case DRM_FORMAT_BGRA5551:
146+
*format = WIN_COLOR_DEPTH_AR5G5B5;
147+
break;
148+
149+
case DRM_FORMAT_XRGB1555:
150+
*format = WIN_COLOR_DEPTH_B5G5R5X1;
151+
break;
152+
153+
case DRM_FORMAT_RGBX5551:
154+
*format = WIN_COLOR_DEPTH_X1B5G5R5;
155+
break;
156+
157+
case DRM_FORMAT_XBGR1555:
158+
*format = WIN_COLOR_DEPTH_R5G5B5X1;
159+
break;
160+
161+
case DRM_FORMAT_BGRX5551:
162+
*format = WIN_COLOR_DEPTH_X1R5G5B5;
163+
break;
164+
165+
case DRM_FORMAT_BGR565:
166+
*format = WIN_COLOR_DEPTH_R5G6B5;
167+
break;
168+
169+
case DRM_FORMAT_BGRA8888:
170+
*format = WIN_COLOR_DEPTH_A8R8G8B8;
171+
break;
172+
173+
case DRM_FORMAT_RGBA8888:
174+
*format = WIN_COLOR_DEPTH_A8B8G8R8;
175+
break;
176+
177+
case DRM_FORMAT_XRGB8888:
178+
*format = WIN_COLOR_DEPTH_B8G8R8X8;
179+
break;
180+
181+
case DRM_FORMAT_XBGR8888:
182+
*format = WIN_COLOR_DEPTH_R8G8B8X8;
131183
break;
132184

133185
case DRM_FORMAT_UYVY:

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