OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

An abstraction library for interfacing EDA tools

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

A Python package to use FPGA development tools programmatically.

FPGA tool performance profiling

Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe

RealtimeIO for LinuxCNC based on an FPGA

Unofficial Yosys WebAssembly packages

Sphinx Extension which generates various types of diagrams from Verilog code.

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

HDL development environment on Nix.

An interactive digital logic simulator with verilog support (Yosys)

A Python-based HDL and framework for silicon-based witchcraft

Example of how to get started with olofk/fusesoc.

Solving Sudokus using open source formal verification tools

Synthesize Verilog to Minecraft redstone

WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.

6502 CPU implementation written in nMigen

A Python library, and CLI utilities, which solves HDL-to-bitstream based on FOSS.

SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA