Brevitas: neural network quantization in PyTorch

Documenting the Xilinx 7-series bit-stream format.

An abstraction library for interfacing EDA tools

Repurposing existing HDL tools to help writing better code

A configurable and approachable tool for FPGA debugging and rapid prototyping.

Limited python / cocotb interface to Xilinx/AMD Vivado simulator.

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

A flexible and scalable development platform for modern FPGA projects.

HDLGen-ChatGPT, works in tandem with ChatGPT chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project

Bazel rules for Xilinx Vivado

Tool for graphically viewing FPGA bitstream files and their connection to FASM features.

FPGA mandelbrot accelerator via high speed/super speed USB

Infinite-ISP Image Signal Processing Pipeline FPGA Binaries for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit and Efinix® Titanium Ti180 J484 Development Kit

A Python-based IP Core Management Infrastructure.

AI High-Performance Solution on FPGA

Python wrapper for Xilinx's XSCT/XSDB console

mirror of https://git.elphel.com/Elphel/ezynq

Visual System Integrator - Accelerate your embedded development

FPGA-accelerated array computing

This project automates process of creating a PYNQ Z1/Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.