Simulator (more accurately: an assembler and an emulator) for Xilinx PicoBlaze, runnable in a browser. That is my Bachelor thesis.

Verilog HDL implementations of adders/subtractor, multiplier, divider and square root. As well as HTML simulations.

A set of PHP files, scripts and database to allow remote users to edit programs, upload code and access the serial port of real microcontrollers.

verilog code for full adder in xilinx vivado with testbench and simulation

half adder code in verilog in xilinx vivado

basic logic gates are implemented using verilog languege and simulation is done in xilinx vivado

A collection of my projects and code created while learning VHDL. This repository tracks my progress in digital logic design and FPGA programming, from basic concepts to more complex circuits.

🔧 Explore Verilog code for a Half Adder with testbench and simulation results, designed for Xilinx Vivado. Perfect for learning digital design fundamentals.

Dionysios Diamantopoulos Web Edition

basic logic gates are implemented using verilog languege and simulation is done in xilinx vivado