SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
A library of VHDL components for Neural Networks
FPGA Cryptography for High-Level Synthesis
Xilinx Virtual Cable (XVC) Server implementation for use with an Arduino UNO/Leonardo
FPGA and firmware images for the USRP2 to operate as a Wireless Firewall (WiFire)
High level synthesis projects and practices
Small project to track things with a waterproof sonar sensor
This demo is intended to demonstrate the FPGA design protection and metering capability provided by the Accelize Distribution Platform.
Custom IP for the Mini-EUSO PDM-DP Zynq system
Hardware accelerator for Image processing in FPGA
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