System Verilog BootCamp
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Jan 21, 2022 - SystemVerilog
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vlsi
Here are 19 public repositories matching this topic...
Basics of UVM via an APB slave
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Jul 2, 2019 - SystemVerilog
Basic ALU testbench written in UVM for experiments
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Aug 28, 2018 - SystemVerilog
Application Specific Integrated Circuit(ASIC)
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Jun 7, 2018 - SystemVerilog
Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
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May 9, 2022 - SystemVerilog
5-stage-Pipeline-CPU with AXI bus
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Nov 7, 2024 - SystemVerilog
asic hardware-designs post-quantum-cryptography vlsi homomorphic-encryption lattice-based-crypto modular-multiplication
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Sep 27, 2022 - SystemVerilog
Verilog implementation of a 4-bit adder/subtractor using combinational logic with testbench and simulation output.
binary verilog vivado systemverilog vlsi adder testbench digital-design subtractor structural-modeling behavioural-modeling behavioural-simulation
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May 28, 2025 - SystemVerilog
Verification environment for beta architecture processor ( implemented in MIT course on edx)
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May 27, 2022 - SystemVerilog
Verilog implementation of an N-bit ALU supporting operations like AND, OR, ADD, SUB, SLT, and functions with complemented inputs. Ideal for CPU design and digital system projects.
asic simulation verilog systemverilog alu vlsi testbench system-verilog digital-design xilinx-vivado behavioural arithmetic-logic-unit behavioural-modelling behavioural-simulation
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May 29, 2025 - SystemVerilog
A SystemVerilog implementation of a 4-bit unsigned array multiplier using structural design. The module computes an 8-bit product from two 4-bit binary inputs by generating partial products and summing them using full adders. Ideal for learning digital design fundamentals and testing with simulators or FPGA synthesis tools.
design digital array verilog systemverilog vlsi testbench system-verilog digital-design computer-organization xilinx-vivado multiplier digital-system-design array-multiplier
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May 29, 2025 - SystemVerilog
Verilog implementation of an N-bit arithmetic/logical shifter and rotator supporting left/right shifts and rotations. Useful for CPU datapaths and digital design applications.
asic verilog systemverilog vlsi system-verilog xilinx-vivado digital-system-design logic-system behavioural-simulation arithmetic-logic-shifter-rotator
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May 29, 2025 - SystemVerilog
Verilog implementation of a synchronous 4-bit up/down decade counter with asynchronous clear, load, and carry-out features. Also includes a 2-decade decimal counter design using two such counters cascaded together. Simulates counting up/down from 00 to 99 with load, increment, and clear operations.
design counter verilog xilinx vivado systemverilog vlsi system-verilog digital-design xilinx-vivado decade-counter digital-system synchoronous-counter testench decimal-counter
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May 30, 2025 - SystemVerilog
Optional Project for the course VLSI in the 8th semester of University.
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Nov 16, 2022 - SystemVerilog
Verilog implementation of an 8-bit bidirectional synchronous shift register with asynchronous clear and parallel load capability. Supports left shift, right shift, no operation, and direct parallel loading via control inputs. Ideal for learning shift register operations and mode control logic.
register verilog vivado vlsi testbench system-verilog shift-register shift digital-design xilinx-vivado digital-system-design
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May 30, 2025 - SystemVerilog
Verilog implementation of an N-bit comparator with outputs for equal, not equal, greater than, less than, greater than or equal, and less than or equal.
simulation verilog vivado vlsi comparator system-verilog digital-design behavioural-simulation behavioural-design n-bit-comparator
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May 28, 2025 - SystemVerilog
SystemVerilog implementation of a Binary to Gray Code Converter in both structural and behavioral styles. Includes a simple testbench for verification. Useful for digital design learners and FPGA developers.
converter binary verilog vivado systemverilog vlsi testbench system-verilog digital-design gray xilinx-vivado graycode digital-system binary-gray-converter xilinxvivado
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Jun 9, 2025 - SystemVerilog
SystemVerilog implementation of an unsigned binary divider for 4-bit inputs using a hardware-friendly algorithm.
simulation array verilog systemverilog vlsi divider testbench system-verilog digital-design xilinx-vivado digital-system-design behavioural-simulation array-divider
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May 29, 2025 - SystemVerilog
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