Machine learning on FPGAs using HLS
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Dec 3, 2025 - Python
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vivado
Here are 25 public repositories matching this topic...
An abstraction library for interfacing EDA tools
fpga simulation vhdl eda verilog xilinx synthesis vivado altera systemverilog icestorm lattice icarus-verilog modelsim ghdl yosys verilator riviera-pro fossi spyglass
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Nov 17, 2025 - Python
Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
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Sep 28, 2025 - Python
A flexible and scalable development platform for modern FPGA projects.
asic fpga ci simulation test vhdl build-automation eda test-automation rtl verilog xilinx synthesis vivado systemverilog implementation vunit
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Nov 24, 2025 - Python
HDLGen-ChatGPT, works in tandem with ChatGPT chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project
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Oct 28, 2024 - Python
Bazel rules for Xilinx Vivado
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Sep 1, 2022 - Python
Example of how to get started with olofk/fusesoc.
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Jul 25, 2021 - Python
Resource Utilization and Latency Estimation for ML on FPGA.
python machine-learning fpga neural-network hls keras prediction pytorch vivado regression-models resource-utilization onnx surrogate-models vitis
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Sep 23, 2025 - Python
Visual System Integrator - Accelerate your embedded development
embedded fpga zynq integration hls accelerator cnn rapid accelerate lenet xilinx vivado sdx rapid-development mpsoc fpga-accelerator high-level-synthesis sdsoc virtex7 xilinx-zynq
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Jun 18, 2018 - Python
This project automates process of creating a PYNQ Z1/Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
python automation fpga vhdl verilog xilinx vivado hardware-designs pynq hdl pynq-z1 pynq-z2 pynq-platform hdlgen-chatgpt
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Mar 2, 2025 - Python
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