A small utility to reverse bit order of the output bitstream generated by Quartus ii before it can be flashed into the FPGA flash memory of the arduino vidor MK4000.

Simulation platform that enables VHDL-style C++ coding. VCD generation for easy debug. VHDL code generation using C preprocessor. Simple risc-V rv32i SoC example, + Risc-V test suite and gcc bare-metal example. Linux (or WSL) / clang or gcc / risc-v toolchain / quartus required

Template to use Vidor 4000k with clean fpga and AVALON Bridge to Nina W-10*

This project demonstrates how to use Arduino’s new MKR Vidor 4000 to build a lock using a Quick Response (QR) code.