#

uart-protocol

Here are 3 public repositories matching this topic...

Thirumavalavasethurayar / Automated-Sequence-Item-Generation-for-Different-Serial-Communication-Protocols

Python script to create sequence item from spreadsheet

python network ip verilog systemverilog canbus uvm testbench uvc uart-protocol protocol-oriented-programming canbus-communications canbus-communication

Updated Apr 24, 2025
SystemVerilog

Unicamp-Odhin / UART

UART Peripheral written in SystemVerilog

hardware verilog uart systemverilog uart-protocol

Updated Aug 12, 2025
SystemVerilog

disabel1a / parametrized-UART

Fully parameterizable uart (data width, clock frequency, parity bit [ON/OFF];[ODD/EVEN], stop bit length, baud rate, seniority [DESC/ASC])

fpga hardware verilog systemverilog uart-protocol seniority baud-rate parity-check parametrized-uart stop-bit-length

Updated Jul 16, 2024
SystemVerilog

Improve this page

Add a description, image, and links to the uart-protocol topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the uart-protocol topic, visit your repo's landing page and select "manage topics."