Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

SystemVerilog compiler and language services

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

80186 compatible SystemVerilog CPU core and FPGA reference design

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

A SystemVerilog language server based on the Slang library.

Introduction to Computer Systems (II), Spring 2021

Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes... now for the first time in opensource on the Host side too! Our project roots for Root Port in 4 ways: 1) openRTL; 2) openBFM with unique SIM setup, way faster than vendor's; 3) openSW stack; 4) one-of-a-kind openBackplane.

A library and command-line tool for querying a Verilog netlist.

利用C++实现针对SystemVerilog的高性能在线编译系统，可将SystemVerilog源代码进行高鲁棒性的词法解析和常见语法分析和部分语义分析，生成可靠Abstract Syntax Tree，并提供Parser解析过程信息、报错信息和变量表，该在线编译系统通过webbenchh压力测试可以实现近万的QPS

Tools based upon slang for language server purpose

UML-JTracing是基于C++20实现，针对于芯片领域常用C++和SystemVerilog两种编程语言自动进行高鲁棒性的词法解析和常见语法分析和语义分析，生成可靠Abstract Syntax Tree，并提供Parser解析过程信息、报错信息和变量表等解析信息，通过自定义数据结构对解析过程进行格式化存储，最终将利用Python实现的UML智能生成器检测到结构化后的解析信息，通过加载解析信息进行自动绘制目标源代码的UML时序图

Hardware accelerated Julia set explorer running on Ultra96

Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)

Hardware description language that tries not to suck

Running verilog on hardware, desktop and the web

[WIP] in-order 5(+2)-stages pipeline MIPS64r6el SoC implementation with peripheral components, simulated with verilator

Designed a Neural Network Generator using C++ and System Verilog