Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
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Updated
Oct 21, 2024 - Verilog
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systemrdl-compiler
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Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
eda verilog systemverilog uvm registers systemrdl register-descriptions systemrdl-compiler fpga-development asic-design
-
Updated
Dec 19, 2024 - Verilog
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