systemrdl-compiler

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Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

asic fpga csr systemverilog registers systemverilog-hdl systemrdl systemrdl-compiler

Import and export IP-XACT XML register models

asic fpga eda ip-xact register-descriptions systemrdl-compiler ipxact

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

This repository is for DEDA class in 2017.

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