Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.

Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.

Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.

Exploring Synopsys(R) synthesis tools

DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino

I2S (Inter-IC Sound) interface module with APB (Advanced Peripheral Bus) interface signals. It has control logic for writing and reading data to/from a 4x32-bit FIFO and generates clock (sck), word select (ws), and serial data (sd) signals for I2S transmission.

Implementation of a MIPS CPU using Verilog.

Master degree project for Synthesis and Optimization of Digital Systems

This repository is about the main project of the course "VLSI System Design". This course is part of my undergraduate studies on University of Thessally - ECE Department located in Volos, Greece.

Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT