#

soc

Here are 18 public repositories matching this topic...

WangXuan95 / USTC-RVSoC

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

cpu fpga riscv rtl verilog systemverilog soc risc-v rv32i softcore

Updated Sep 14, 2023
SystemVerilog

dpretet / axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

Updated Apr 10, 2025
SystemVerilog

merledu / azadi-soc

Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

riscv systemverilog soc ibex

Updated Aug 28, 2023
SystemVerilog

SoC-DV

PacoReinaCampo / SoC-DV

System on Chip verified with UVM/OSVVM/FV

soc uvm formal-verification osvvm risc-v openrisc msp340

Updated Apr 16, 2025
SystemVerilog

SoC-RISCV

PacoReinaCampo / SoC-RISCV

System on Chip with RISCV-32 / RISCV-64 / RISCV-128

simd soc risc-v misd

Updated Apr 16, 2025
SystemVerilog

SoC-NTM

PacoReinaCampo / SoC-NTM

Neural Turing Machine for a System on Chip verified with UVM/OSVVM/FV

neural-network soc neural-turing-machine differentiable-neural-computer

Updated Apr 16, 2025
SystemVerilog

SoC-MSP430

PacoReinaCampo / SoC-MSP430

System on Chip with MSP430-16

simd msp430 soc misd

Updated Apr 16, 2025
SystemVerilog

pConst / xilinx_max_power

Stress test power subsystem of your Xilinx FPGA board

development board fpga test power verilog xilinx systemverilog cooling soc shift-register digilent arty ultrascale zinq

Updated Apr 8, 2018
SystemVerilog

DatNguyen97-VN / cellrv32

A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.

microcontroller systemverilog soc risc-v system-on-chip

Updated Mar 6, 2025
SystemVerilog

cheyao / Achieve-Core

RISC-V SoC + OS

core verilog soc risc-v

Updated Feb 26, 2023
SystemVerilog

2uger / petalinux_notes

Notes after working with Zynq platform using vivado and petalinux

linux xilinx vivado systemverilog soc petalinux dma zynq-7000 axi-stream

Updated Feb 26, 2024
SystemVerilog

Teimir / Ether-Simple-Proc

Репозиторий пэт проекта 8-и битного процессора

cpu systemverilog hdl soc cpu-simulator soc-design

Updated Apr 5, 2025
SystemVerilog

SoC-OR1K

PacoReinaCampo / SoC-OR1K

System on Chip with OpenRISC-32 / OpenRISC-64

simd soc openrisc misd

Updated Apr 16, 2025
SystemVerilog

JasonBrave / MicroSoC

RISC-V SoC

microcontroller riscv verilog uart systemverilog soc risc-v system-on-chip

Updated Sep 4, 2023
SystemVerilog

strwdr / MaximatorZXSpectrum

ZX Spectrum implementation for maximator board

board fpga verilog zx-spectrum nios hdl soc zx max10 maximator

Updated Jan 17, 2023
SystemVerilog

Rafa350 / fpga-uart

UART implementation for my RISCV project

fpga verilog uart soc

Updated Jan 10, 2021
SystemVerilog

OrsuVenkataKrishnaiah1235 / System-Verilog

"Mastering SystemVerilog: From Fundamentals to Advanced Programming Techniques"

asic verification verilog systemverilog soc sv vlsi-design systemverilog-examples systemverilog-problems

Updated Mar 31, 2023
SystemVerilog

0xD503 / SPI-Interface

SPI Interface RTL Description

fpga ip spi soc fpga-soc serial-communication serial-communications

Updated May 21, 2019
SystemVerilog

Improve this page

Add a description, image, and links to the soc topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the soc topic, visit your repo's landing page and select "manage topics."