A very simple computer written in Verilog, with a Python test bench

Yet Another SAP-1 based 8-bit computer

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

Code, documentation, schematics, notes for my Ben Eater inspired breadboard computer and emulator

Documentation of my 8-bit computer build

The Simple-As-Possible (SAP)-1 computer is a very basic model of a microprocessor explained by Albert Paul Malvino. The SAP-1 design contains the basic necessities for a functional Microprocessor. Its primary purpose is to develop a basic understanding of how a microprocessor works, interacts with memory and other parts of the system like input …

Verilog implementation of SAP-1 computer architecture

A C++ Implementation of X-Bit Computer SAP-X Architecture Virtualization

An Emulator for the SAP-1 Computer

Emulator of my 8-bit-computer

SAP-1 implementation in VHDL for the Sipeed Tang Nano 9k

SAP-1 emulator written in Rust

Not Quite Simple As Possible breadboard computer

Il mio breadboard computer TTL a 8 bit basato sulla realizzazione di Ben Eater e sui miglioramenti di Tom Nisbet