SCR1 is a high-quality open-source RISC-V MCU core in Verilog

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

A Single Cycle Risc-V 32 bit CPU

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

RISCV CPU implementation in SystemVerilog

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

RISC-V implementation of RV32I for FPGA board Tang Nano 20K utilizing on-board burst SDRAM, flash and SD card

A pipelined, in-order implementation of the RV32I ISA

Simple RISC-V Pipelined processor implemented on SystemVerilog.

A repository consisting of all the project files and codes for RISC-V Processor design using Transaction Level Verilog.

Minimalistic RV32I RISC-V Processor in System Verilog

This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog

This is a Single Cycle processor running the RV32I implementation, hence a 32-bit CPU, written in SystemVerilog.

ucrv32 is a simple educational RV32I microcontroller featuring a 5-stage pipeline architecture. Written in SystemVerilog and equipped with simulation support via Verilator, it offers a practical platform for learning digital design and computer architecture concepts.

Basic RV32I RISC-V CPU Implementation

Processor Design of RV32I 5-Stage Pipelined CPU

Soft-core RISC-V CPU

This is an RV32_IM riscv cpu core. Its a non-pipelined core with MULW instruction alone from M extension.

Processor Design of RV32I Single Cycle CPU