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questa-sim

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gopro-uvm-rtl-verification / Async-Fifo-Cdc-Uvm-Verification

UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.

makefile verification vcs systemverilog fifo cdc uvm testbench sva metastability functional-coverage async-fifo questa-sim

Updated Aug 22, 2025
SystemVerilog

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