This project automates process of creating a PYNQ Z1/Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
python automation fpga vhdl verilog xilinx vivado hardware-designs pynq hdl pynq-z1 pynq-z2 pynq-platform hdlgen-chatgpt
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Updated
Mar 2, 2025 - Python