OpenTitan Flash Ctrl IP block

OpenTitan UART IP - Full duplex serial communication peripheral with programmable baud rate, RX/TX buffers, and interrupt support

This document specifies the OTP MACRO hardware IP functionality.

OpenTitan Rv Core Ibex IP block

System Reset Controller (sysrst_ctrl) that provides programmable hardware-level responses to trusted IOs and basic board-level reset sequencing capabilities

Analog to Digital Converter Control Interface

The mailbox IP block in the OpenTitan Integrated design implements a request-response channel that the host System-on-Chip (SoC) may use to request security ser

ROM controller (rom_ctrl) is the connection between the chip and its ROM

Debugging in RISC-V can be done using one of the following mechanisms:

OpenTitan Prim Xilinx IP block

Cryptographically Secure Random Number Generator (CSRNG)

Keccak Message Authentication Code (KMAC) and Secure Hashing Algorithm 3 (SHA3)

Entropy Distribution Network (EDN) interfaces to the CSRNG IP module

OpenTitan Prim Xilinx Ultrascale IP block

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SRAM memory controller

OpenTitan Keymgr Dpe IP block

The Direct Memory Access (DMA) controller is a peripheral within the OpenTitan system-on-chip (SoC).

OpenTitan Prim Generic IP block

I2C controller