network-stack

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UDP/IP network stack from scratch (v1) - MII PHY, MAC/IP/UDP parsing in VHDL. First working version with <2μs latency.

fpga udp vhdl xilinx low-latency ethernet mii trading-systems network-stack ip-stack artix-7

UDP parser v2 - Improved MAC filtering and IP checksum validation. Fixed preamble stripping issues.

fpga udp vhdl xilinx low-latency ethernet mii network-stack ip-stack artix-7

UDP parser v5 FINAL - Real-time byte-by-byte architecture. 1% → 100% success rate. Production-ready with comprehensive XDC constraints.

real-time fpga udp vhdl xilinx low-latency ethernet production-ready mii trading-systems network-stack ip-stack artix-7

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