NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

Single Cycle 32 bit MIPS

SUSTech CS202/CS214 Computer Organization Project. Streams Bad Apple.

MIPS32 CPU implemented in SystemVerilog, with superscalar and branch prediction support

MIPS CPU in verilog

A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.

32-bit single cycle CPU design and implementation of the "Asteroids" arcade game for this CPU in Assembly and C.

A complete hardware description of a non-pipeline MIPS processor in SystemVerilog that can execute integer assembly code implemented on the Altera DE2-115 FPGA.

A synthesizable simplified MIPS written in System Verilog

MIPS architecure processor on Intel FPGA.

CPU コアの基礎を学ぶ

A Developer version MIPS processor.

Mips Multi-Cycle, Computer Architecture course, University of Tehran

This is a modified version of the 32-bit MIPS microprocessor. Please refer to "manual.pdf" for more information.

MIPS written in System Verilog

It's a simple verilog based MIPS microarchitecture hardware design.

A complete hardware description of a pipeline MIPS processor in SystemVerilog that can execute integer assembly code implemented on the Altera DE2-115 FPGA. It also has the ALMa Mips Mounter built-in.

Mips Single-Cycle, Computer Architecture course, University of Tehran