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mips-architecture

Here are 77 public repositories matching this topic...

neelkshah / MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

verilog microprocessor computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project

Updated Apr 3, 2020
Verilog

RomeoMe5 / DDLM

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Updated Sep 15, 2023
Verilog

ljlin / MIPS48PipelineCPU

5 stage pipelined MIPS-32 processor

cpu mips architecture verilog mips-architecture

Updated Apr 20, 2020
Verilog

SilenceX12138 / MIPS-Microsystems

A computer system containing CPU, OS and Compiler under MIPS architecture.

compiler operating-system computer-architecture mips-architecture

Updated Sep 9, 2021
Verilog

maze1377 / pipeline-mips-verilog

A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall

mips verilog mips-architecture mips32 pipline control-hazards mips-instruction data-hazards pipeline-mips-verilog

Updated Jan 28, 2025
Verilog

tjsparks5 / Pipelined-MIPS-Processor

Pipelined MIPS architecture created in Verilog. Includes data forwarding and hazard detection.

python rtl verilog mips-architecture

Updated Apr 1, 2018
Verilog

amirHosseinEz / MIPS-architecture

MIPS architecture implemented in Verilog.

hardware mips verilog mips-architecture

Updated Aug 2, 2023
Verilog

LIU42 / Processor

《计算机组成原理》课程设计，基于 MIPS 的流水线 CPU 系统设计。

cpu fpga pipeline mips architecture verilog course-project computer-architecture mips-architecture mips-processor homework-project

Updated Aug 27, 2025
Verilog

mongrelgem / cMIPS

A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.

processor hardware-designs verilog-hdl mips-architecture mips-processor vhdl-code

Updated Sep 3, 2019
Verilog

RISC-Processor

Ecolash / RISC-Processor

𝗠𝗶𝗻𝗶𝗠𝗜𝗣𝗦 | 𝗥𝗜𝗦𝗖 𝗣𝗿𝗼𝗰𝗲𝘀𝘀𝗼𝗿 𝗗𝗲𝘀𝗶𝗴𝗻 | CS39001 𝗖𝗼𝘂𝗿𝘀𝗲 𝗣𝗿𝗼𝗷𝗲𝗰𝘁

pipeline processor assembler vivado hardware-designs assembly-language-programming computer-architecture verilog-hdl instruction-set-architecture mips-architecture control-unit fpga-programming controlpath computer-organization-and-design risc-architecture datapath-design

Updated Sep 14, 2025
Verilog

akankshac-073 / MIPS-5-stage-pipelined-control-and-datapath

Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding cont…

verilog computer-architecture mips-architecture mips-processor mips32 pipelined-processors mips-pipline-processor-verilog

Updated Mar 22, 2022
Verilog

Choaib-ELMADI / working-with-fpga-and-mips

A collection of practical sessions exploring FPGA programming and MIPS-based systems using the ALTERA Cyclone V DE-1 SoC board.

fpga mips vhdl embedded-systems mips-assembly soc fpga-soc mips-architecture fpga-board fpga-programming

Updated Apr 7, 2025
Verilog

susiejojo / MIPS_processor

A simple MIPS processor implemented using Verilog capable of supporting basic I,J and R type instructions. Built using Xilinx Vivado 2019.1

mips processor verilog mips-architecture

Updated May 20, 2020
Verilog

ukashasohail / MIPS_32bit_SCDP_Verilog

An implementation of 32-bits MIPS Single Cycle Datapath in Verilog HDL.

mips mips-assembly verilog verilog-hdl mips-architecture mips32 verilog-project verilog-code

Updated Feb 14, 2021
Verilog

sinasoltani123 / 32-bit-pipelined-MIPS-processor-implemented-using-Verilog-with-booth-multiplication-algorithm

32-bit pipelined MIPS CPU using Verilog with booth multiplication algorithm (faster multiplication in hardware). Xilinx Sesign Suite

cpu mips verilog xilinx mips32cpu mips-architecture

Updated Jul 16, 2022
Verilog

shivamkundan / MIPS_CPU

Implementation of a MIPS CPU using Verilog.

mips mips-assembly verilog synopsys cadence-virtuoso mips-architecture mips32

Updated May 19, 2023
Verilog

HuangDave / MIPS

Single-Cycle and 5-stage Pipelined SoC

rtl verilog fpga-soc mips-architecture mips-processor fpga-programming

Updated May 26, 2018
Verilog

oaxelou / ce232

Computer Organization and Design (2nd year - 3rd semester)

assembly mips-assembly verilog cache-control mips-architecture

Updated Jan 5, 2018
Verilog

HassanTaqiEddin / ASIC-Design-And-Verification-Project

Pipelined Processor, Cycle Accurate Simulator, UVM, Automation

error-monitoring pipeline assembler verification verilog computer-architecture cycle-accurate uvm mips-architecture memory-handler functional-modelling

Updated Oct 9, 2024
Verilog

Sh-Zh-7 / tiny-CPU

Tiny series: A handwritten CPU of MIPS instruction set.

cpu-model mips-architecture computer-organization tiny-series

Updated Mar 27, 2020
Verilog

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