scs16 is a micro controller core, with 16b data path and single cycle instructions, developed started at 2003, I'm making the 2008 version public. this core is very efficient replacing FSM and making flows programmable instead of hardcoded. Project by Max Nigri
this is the results of 2 years of development of the first logic simulator that is based on HW instead of SW. Project by Max Nigri
Hardware implementation of a JPEG encoder for FPGA/ASIC, developed as an academic project in the Advanced Logic Design course (Hebrew University, 2006–2017). Project by Max Nigri
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