Toolset to capture, simulate, synthesize and verify graph models
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Updated
Oct 15, 2024 - Java
Toolset to capture, simulate, synthesize and verify graph models
An open-source design automation framework for Field-coupled Nanotechnologies
OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.
Logic synthesis and ABC based optimization
A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""
This project will be the beginning of my research life!
Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
C++ parsing library for simple formats used in logic synthesis and formal verification
Wei-Shen's Fork 2023 Fall Logic Synthesis and Verification: Programming Assignments
C++ header-only ESOP library
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Logic Locking Attacks via Synthesis Tuning
This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.
Efficient resubstitution-based approximate logic synthesis
Automated conversion from CHP to PRS using syntax-directed translation
Showcase examples for EPFL logic synthesis libraries
A boolean matcher that computes the NPN canonical representative for a given boolean function.
Extract leaf level RTL modules from OpenROAD and collect PPA numbers generated by Yosys
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