logic-synthesis
Here are 59 public repositories matching this topic...
Wei-Shen's Fork 2023 Fall Logic Synthesis and Verification: Programming Assignments
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May 19, 2024 - C
This article describes how embedded languages and recursion can be used to create a tool that synthesizes a relatively efficient logical circuit for any chosen permutation of the set of all bit vectors of some fixed length.
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May 16, 2021 - Jupyter Notebook
An approach to algorithm optimization through circuit minimization techniques.
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Apr 10, 2017 - Java
This project will be the beginning of my research life!
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Aug 26, 2024 - C++
Code repository for the IWLS 2021 Programming Contest
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Aug 7, 2023 - Python
An application using Cadence IC Package
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Feb 12, 2023 - Verilog
A boolean matcher that computes the NPN canonical representative for a given boolean function.
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Mar 24, 2024 - C++
DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization
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Jan 23, 2020 - Python
CELLO - Cell Genetic Circuit Design Automation. Python code built from the ground up, which branched off into the repositories Cello-V3-Core and UCFormatter.
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Jun 8, 2023 - Python
Extract leaf level RTL modules from OpenROAD and collect PPA numbers generated by Yosys
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Feb 28, 2024 - Verilog
MATLAB and HDL models of ACA-CSU approximate adders
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May 17, 2021 - Verilog
An implementation of binary decision tree with fringe-features extraction.
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Aug 8, 2023 - Python
To generate an electrical circuit from the given input and output boolean values.
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Dec 7, 2023 - Python
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Logic Locking Attacks via Synthesis Tuning
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May 13, 2024 - Verilog
C++ header-only And-Inverter graph (AIG) library
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Mar 26, 2018 - C++
Logic synthesis and verification framework
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Nov 13, 2017 - C++
Approximate Logic Synthesis and Bi-Decomposition of Sum Of Products forms
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Nov 9, 2020 - C
This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.
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May 10, 2024 - Verilog
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