An application using Cadence IC Package
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Updated
Feb 12, 2023 - Verilog
An application using Cadence IC Package
Extract leaf level RTL modules from OpenROAD and collect PPA numbers generated by Yosys
MATLAB and HDL models of ACA-CSU approximate adders
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Logic Locking Attacks via Synthesis Tuning
This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.
An approximate logic synthesis tool under the maximum error constraint
Highly efficient delay-driven approximate logic synthesis
Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction
Benchmarks for Approximate Circuit Synthesis
The Verilog source code for DRUM approximate multiplier.
An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
DATC RDF
EDA physical synthesis optimization kit
OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.
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