ip-core
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Synthesizable SystemVerilog IP-Core of the I2S Receiver
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Jun 7, 2020 - SystemVerilog
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
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Jun 7, 2020 - SystemVerilog
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
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Jun 6, 2020 - SystemVerilog
Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency.
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Oct 8, 2025 - SystemVerilog
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