hardware design of universal NPU(CNN accelerator) for various convolution neural network
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Mar 5, 2025 - Verilog
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hardware-design
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Verilog-based vending machine controller IP core, supporting multi-clock domain operation, inventory management, and currency denominations. Built with the APB protocol for efficient configuration, it offers smart change calculation and robust error handling. Developed in the SURE ProEd internship training with experts.
embedded-systems error-handling verilog memory-management vlsi digital-systems fpga-development vlsi-design hardware-design internship-project apb-protocol sure-trust vending-machine-controller sure-proed multi-clock-domain
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Apr 25, 2025 - Verilog
Design and Development of AES Encryption and Decryption Modules in Verilog HDL for AES128, AES192, and AES256 Algorithms.
security cryptography fpga aes-256 aes-128 aes-192 aes-encryption verilog-hdl data-encryption data-security advanced-encryption-standard aes-decryption fpga-development algorithm-implementation hardware-design
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May 14, 2024 - Verilog
Sumador de dos números de dos dígitos cada uno codificados en ASCII estándar en 7 bits. Restricción: realizar la suma en binario natural.
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Dec 19, 2021 - Verilog
Modular Verilog designs of a 4-bit CPU and its components, including ALU, register, and datapath.
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Apr 16, 2025 - Verilog
Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)
c assembly spike verilog gtkwave soc yosys risc-v iverilog gate-level-simulation hardware-design chipcron
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May 8, 2024 - Verilog
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