gray-code

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rohit-kumarpanda / fifo-verilog

Parameterized Synchronous and Asynchronous FIFO implementations in Verilog HDL with Gray-code pointer synchronization, CDC handling, and Vivado verification.

verilog fifo cdc vlsi verilog-hdl digital-design xilinx-vivado gray-code clock-domain-crossing asynchronous-fifo rtl-design synchronous-fifo

Updated Jul 29, 2026
Verilog

lucianobajr / Introduction-to-Logic-Systems-2P

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Basic tools, methods and procedures to design combinational and sequential digital circuits and systems. Topics include number systems, Boolean algebra, logic minimization, circuit design, memory elements, and finite state machine design.

finite-state-machine combinational-logic sequential-logic gray-code

Updated Dec 6, 2019
Verilog

VLSI-Shubh / Asynchronous-FIFO

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Production-ready asynchronous FIFO buffer with independent read/write clock domains for safe CDC operations. Features Gray code pointers, dual flip-flop synchronizers, metastability prevention, and parameterized design. Essential for SoC inter-module communication and multi-clock systems.

verilog metastability gray-code clock-domain-crossing vlsi-design soc-design

Updated Dec 5, 2025
Verilog

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