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functional-coverage

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Language: Verilog
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All 8 Python 2 SystemVerilog 2 Verilog 2 Scala 1 VHDL 1

Noamv7 / Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

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This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

verification matrix-multiplication verilog systemverilog questasim logic-design sva systolic-arrays amba-apb functional-coverage chip-design
  • Updated Jun 26, 2024
  • Verilog

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