Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators
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Updated
Dec 26, 2023 - Verilog
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function-generator
Here are 5 public repositories matching this topic...
Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.
fpga
radix-4
function-generator
baud-rate
digital-logic-design
clock-generator
digital-logic-design-lab
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Updated
Aug 3, 2022 - Verilog
Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.
fpga
radix-4
function-generator
baud-rate
digital-logic-design
clock-generator
digital-logic-design-lab
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Updated
Aug 3, 2022 - Verilog
Projects of the digital logic design lab (Fall01) at the University of Tehran.
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Updated
Oct 6, 2023 - Verilog
a project for Digital Logic Design Lab S96 at University of Tehran - mirror of https://gitlab.com/hadi_sfr/Function-Generator-verilog
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Updated
Aug 13, 2018 - Verilog
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