A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.

This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.

A VHDL-based VGA driver to display 256 different colors on a monitor.

Practices related to the fundamental level of the programming language Verilog.

A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.

This repo contains documentation of the "VSD Open On-Chip Clock Multiplier (PLL) on OSU180" tutorial.

Xilinx Spartan-3E FPGA; taximeter, stopwatch, etc.; verilog

A simple frequency doubler