Discover and create logic circuits
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Feb 11, 2023 - JavaScript
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flip-flop
Here are 36 public repositories matching this topic...
Flip flop setup, hold & metastability explorer tool
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Jul 12, 2026 - Jupyter Notebook
Materials for the Computer Science course, Digital Design (Logic Circuits)
counter memory decoding karnaugh-map logic-gates boolean-algebra multiplexer adder shift-register registers digital-design digital-systems canonical-forms flip-flop combinational-logic sequential-logic number-systems subtractor logic-circuits programmable-logic
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Apr 25, 2022 - C++
FuzzyNSGA-II-Algorithm (Fuzzy adaptive optimisation method)
genetic-algorithm power genetic-algorithms fuzzy-logic fuzzy-sets nsga-ii nsga2 mosfet-transistor flip-flop hspice mosfet non-dominated-solutions d-flipflop non-dominated-sorting flip-flops hspice-model non-dominating-sorting mosfets fuzzy-nsga-ii fnsga-ii
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Jul 2, 2022 - MATLAB
An eurorack logic module with several logic functions and a clock divider mode. Build around an arduino nano. So could be reprogrammed.
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Dec 19, 2023 - C++
💻 Repositório para Disciplina EEL5105 - Circuitos e Técnicas Digitais - UFSC
language counter fsm register digital hardware clock timer machine vhdl circuits description sequential multiplexer techniques quartus flip-flop multisim latch combinational
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Apr 3, 2020 - VHDL
Implementaciones para diseño de sistemas digitales, comenzando por Flip Flops, registros, autómatas (Máquinas de Moore y Máquinas de Mealy), memorias ROM y sensores de presencia, utilizando para cada uno de estos, distintos contadores (anillo, década, etc).
constants counter vhdl ipn galaxy galaxy-project registro contador moore-to-mealy digital-design mealy-machine escom flip-flop secuenciales moore-machine marquesina gal22v10 rom-memories
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Jun 10, 2017 - VHDL
A 12-hour digital clock with AM/PM indicator built using fundamental digital logic. Implemented in both Proteus (D flip-flops) and on a physical breadboard (7490 counters), featuring a 1Hz 555 timer, 7-segment displays, and custom reset logic.
breadboard proteus flip-flop educational-project circuit-design digital-logic-design electronics-projects 7-segment-display
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Jun 28, 2025
Download my Redstone World: https://www.planetminecraft.com/project/redstone-circuits-6024948/
world ram binary memory clock cycle redstone ticks rom minecraft-resourcepack flip-flop half-adder latch combinational-circuit full-adder sequential-circuit full-subtractor half-subtractor
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Aug 20, 2023 - Python
Sequential circuits in Verilog — Flip-Flops, Registers, Counters, Shift Registers and Synchronous SRAM. Step 3 of 8 in a VLSI portfolio roadmap building to a 16-bit pipelined RISC processor.
fpga verilog sram counters vlsi shift-register registers digital-design flip-flop sequential-circuits rtl-design
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Jul 6, 2026 - Verilog
NYCU 2024 Fall Physical Design Automation(PDA) 陽明交大 陳宏明 實體設計自動化
cpp eda banking simulated-annealing flip-flop floorplan global-routing co-optimization nycu sequence-pair nycu-course corner-stitching bstartree
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Jun 27, 2026 - C++
4-player digital quiz buzzer built in Logisim Evolution — first-press priority lockout using AND gates + SR latches, plus a countdown answer timer with auto-reset.
computer-engineering digital-logic academic-project logisim digital-design flip-flop combinational-logic sequential-circuits sr-latch quiz-buzzer-system
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Jul 26, 2026
⏱️ A step-by-step Logisim Evolution guide for building a digital stopwatch – COS10004 Assignment 1 (2024).
buffer stopwatch assignment buffers logic-gates cos logic-circuit stopwatch-application flip-flop swinburne flip-flops 2024 cos10004
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Jan 24, 2026
Transistor based flip-flop Circuit designed in KiCad.
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Apr 4, 2026
This MPLAB X Melody code example shows how to make an LED blink using the Configurable Custom Logic (CCL) found in the AVR® DB. The CCL is configured as a toggling J-K flip-flop. The toggling is a result of a timer event.
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Jul 2, 2023 - C
This GitHub repository contains coursework projects related to computer systems design. It includes various assignments and projects that cover topics such as digital logic design, computer architecture, and hardware description languages.
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Jul 25, 2023 - VHDL
Flip-Flop solutions written in Go
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Jul 17, 2026 - Go
Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)
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Dec 25, 2022 - Verilog
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