Verilog implementation of a synchronous 4-bit up/down decade counter with asynchronous clear, load, and carry-out features. Also includes a 2-decade decimal counter design using two such counters cascaded together. Simulates counting up/down from 00 to 99 with load, increment, and clear operations.
design counter verilog xilinx vivado systemverilog vlsi system-verilog digital-design xilinx-vivado decade-counter digital-system synchoronous-counter testench decimal-counter
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Updated
May 30, 2025 - SystemVerilog