Wrappers for open source FPU hardware implementations.

A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.

Systolic-array based Deep Learning Accelerator generator

Brainfxxk Processor written Scala(Chisel)

Example of composite video generation with Chisel (B/W for now)

(WIP) NES emulator running on FPGA implemented in scala(w/ chisel)

Workbench of nju-mips, this repo implements a ready-to-work framework for CPU development. It uses differential testing to help find implementation bugs.

Chisel3 examples

Implementation of a Neural Network in Chisel.

Multicycle processor in Chisel3