ASIC implementation flow infrastructure, successor to OpenLane
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Jun 8, 2026 - Python
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chip-design
Here are 13 public repositories matching this topic...
Skywater 130nm Klayout Device Generators PDK
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Jul 12, 2024 - Python
VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.
digital verilog hdl yosys iverilog ai-agents rtl-design chip-design llm-agents eda-automator degital-design claude-code-skills claude-code-skill
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May 25, 2026 - Python
Multi-agent RISC-V verification and test-generation framework for AI-assisted RTL, ISS, compliance, coverage, and debug workflows.
machine-learning ai simulation verification eda riscv rtl verilog systemverilog multi-agent-systems digital-design red-teaming hardware-verification chip-design agentic-ai
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May 7, 2026 - Python
Model Context Protocol (MCP) server for OpenROAD
python mcp eda vlsi physical-design openroad asic-design ai-tools chip-design model-context-protocol fastmcp
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Jun 5, 2026 - Python
Autonomous LLM agent for hardware design — natural language to GDSII via Verilog generation, simulation, and OpenROAD synthesis
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May 19, 2026 - Python
AI-powered Verilog/SystemVerilog MCP Server for Claude Code: generate testbenches, lint RTL code, and scaffold UVM verification environments
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May 17, 2026 - Python
Spectral Graph + Simulated Annealing macro placement engine for the Partcl x HRT Macro Placement Challenge 2026.
python competition optimization numpy eda graph-theory scipy simulated-annealing vlsi electronic-design-automation chip-design spectral-graph macro-placement
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Apr 9, 2026 - Python
Simulated a realistic chip design problem (IR drop) and solved it using end-to-end machine learning:
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Jul 31, 2025 - Python
build custom asics and fpga's using llms.
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Jan 28, 2025 - Python
Leverage artificial intelligence in mixed-signal and SoC chip design workflows to produce baseband modem chips
open-source ai artificial-intelligence computer-engineering hardware-designs cellular-network integrated-circuits baseband 5g analog-design 4g-lte mixed-signal-chips chip-design
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Feb 20, 2026 - Python
SA-Net: Net-aware macro placement via legalization + simulated annealing | Partcl × HRT Challenge 2026
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May 21, 2026 - Python
Lightweight mock EDA signoff flow: parse STA timing reports, summarize violations, and visualize slack distribution.
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Jan 7, 2026 - Python
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