This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
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Oct 19, 2023 - SystemVerilog
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async-fifo
Here are 14 public repositories matching this topic...
UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.
makefile verification vcs systemverilog fifo cdc uvm testbench sva metastability functional-coverage async-fifo questa-sim
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Aug 22, 2025 - SystemVerilog
The repository documents my exploration of essential communication protocols in digital systems. I acknowledge the YouTube channel "All About VLSI" for their insightful workshops and sessions that supported my understanding of protocols
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Mar 23, 2026 - C++
ITCH parser v3 - Async FIFO with gray code CDC. 100% reliability. Code reduction: 677→395 lines (41% simpler).
fpga vhdl xilinx low-latency protocol-parser production-ready cdc trading-systems gray-code nasdaq-itch artix-7 async-fifo
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Jan 24, 2026 - VHDL
Asynchronous FIFO design in SystemVerilog and testbench
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Jul 22, 2026 - SystemVerilog
Parameterized dual-clock asynchronous FIFO designed in Verilog for safe Clock Domain Crossing (CDC). Implements Gray-code pointer encoding, 2-flip-flop synchronizers, and conservative full/empty flag logic following Cummings SNUG 2002 architecture. Verified with a 600-line self-checking reference testbench and SVA protocol assertions across 7 test.
verilog icarus-verilog cdc vlsi yosys digital-design clock-domain-crossing async-fifo systemverilog-assertions
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Jul 22, 2026 - Verilog
Learning-oriented asynchronous FIFO RTL with CDC constraints, wrappers, simulation/formal checks, and PYNQ-Z2 demo
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Jun 27, 2026 - SystemVerilog
A parameterizable Asynchronous FIFO RTL design verified using a custom UVM-style Object-Oriented testbench. Features 100% functional coverage, cycle-accurate timing, and SystemVerilog Assertions (SVA) for CDC protocol compliance.
fpga verification fifo cdc vlsi testbench verilog-hdl digital-design systemverilog-hdl clock-domain-crossing functional-verification asic-design rtl-design uvm-verification async-fifo
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May 16, 2026 - SystemVerilog
UVM verification of an Asynchronous FIFO with SVA assertions, and functional coverage
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Jun 2, 2026 - SystemVerilog
Parameterized asynchronous FIFO UVM 1.2 verification platform with boundary, CDC, and reset regression.
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Jul 20, 2026 - SystemVerilog
Dual-clock asynchronous FIFO in SystemVerilog with layered verification: constrained-random testbench, functional coverage, SVA, SymbiYosys formal spec
verification systemverilog icarus-verilog formal-verification constrained-random sva clock-domain-crossing async-fifo
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Jul 12, 2026 - SystemVerilog
Asynchronous FIFO - dual-clock gray-pointer FIFO in Verilog with industry-style structure
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May 24, 2026 - Verilog
CDC-safe asynchronous FIFO in SystemVerilog with Gray pointers, 2FF synchronizers, SVA, and reproducible simulation/synthesis flows.
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Feb 23, 2026 - Verilog
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