asic-design

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Here are 15 public repositories matching this topic...

hughperkins / VeriGPU

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OpenSource GPU, in Verilog, loosely based on RISC-V ISA

machine-learning gpu verification verilog gpu-acceleration hardware-designs risc-v asic-design risc-v-assembly

Updated Nov 22, 2024
SystemVerilog

chipsalliance / Cores-VeeR-EH1

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VeeR EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer

Updated May 29, 2023
SystemVerilog

chipsalliance / Cores-VeeR-EL2

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VeeR EL2 Core

fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2

Updated Apr 29, 2025
SystemVerilog

dpretet / axi-crossbar

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An AXI4 crossbar implementation in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

Updated May 1, 2025
SystemVerilog

KastnerRG / cgra4ml

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An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

asic ai fpga neural-network cnn dnn verilog systemverilog axi-stream asic-design hls4ml

Updated Apr 28, 2025
SystemVerilog

dpretet / friscv

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RISCV CPU implementation in SystemVerilog

asic fpga assembler riscv verilog systemverilog fpga-soc risc-v rv32i crossbar axi4 axi4-protocol asic-design riscv-cpu

Updated Oct 8, 2024
SystemVerilog

dpretet / bster

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Implementation of a binary search tree algorithm in a FPGA/ASIC IP

asic fpga ip verilog binary-tree systemverilog binary-trees bst fpga-accelerator bstree asic-design svut

Updated Sep 5, 2021
SystemVerilog

rubinsteina13 / SV_I2S_RX_CORE

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Synthesizable SystemVerilog IP-Core of the I2S Receiver

fpga verilog systemverilog hdl system-verilog cpld i2s i2s-dac ip-core asic-design

Updated Jun 7, 2020
SystemVerilog

williaml33moore / bathtub

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BDD Gherkin implementation in native SystemVerilog, based on UVM.

asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification

Updated Nov 16, 2024
SystemVerilog

rubinsteina13 / SV_CLARKE_TRANSFORMATION_CORES

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Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation

fpga verilog systemverilog digital-signal-processing digital-design cpld ip-core asic-design

Updated Jun 7, 2020
SystemVerilog

skipfie / CPEN211

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CPEN 211: Introduction to Microcomputers 2022W1 with Prof. Lis

finite-state-machine ubc systemverilog university-course asic-design ubc-engineering datapath-design

Updated Oct 3, 2023
SystemVerilog

SKpro-glitch / Parallel_Multiplier

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Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.

asic fpga rtl systemverilog verilog-hdl xilinx-vivado multiplier fpga-programming vlsi-design asic-design rtl-design parallel-multiplication systemverilog-test-bench register-transfer-level

Updated Dec 13, 2024
SystemVerilog

kagandikmen / TPU.sv

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Google TPU rebuilt in SystemVerilog: Anatomy of a powerhouse

asic hardware-acceleration asic-design ai-acceleration ai-processor

Updated Oct 12, 2024
SystemVerilog

rubinsteina13 / SV_DSM_CORE

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Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator

fpga verilog digital-signal-processing system-verilog cpld dac ip-core asic-design

Updated Jun 6, 2020
SystemVerilog

Datum-Technology-Corporation / mio_demo

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Moore.io Demo Project

asic fpga uvm digital-design asic-verification design-verification asic-design uvm-verification

Updated Mar 29, 2023
SystemVerilog

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asic-design

Here are 15 public repositories matching this topic...

hughperkins / VeriGPU

chipsalliance / Cores-VeeR-EH1

chipsalliance / Cores-VeeR-EL2

dpretet / axi-crossbar

KastnerRG / cgra4ml

dpretet / friscv

dpretet / bster

rubinsteina13 / SV_I2S_RX_CORE

williaml33moore / bathtub

rubinsteina13 / SV_CLARKE_TRANSFORMATION_CORES

skipfie / CPEN211

SKpro-glitch / Parallel_Multiplier

kagandikmen / TPU.sv

rubinsteina13 / SV_DSM_CORE

Datum-Technology-Corporation / mio_demo

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