ansibleplaybookbundle / ansible-playbook-bundle Star 140 Code Issues Pull requests THIS REPO IS MIGRATING: https://github.com/automationbroker/apb python docker metadata openshift playbook ansible-roles ansible-playbook-bundles apb ansible-service-broker meta-containers Updated Jul 23, 2018 Python
SystemRDL / PeakRDL Star 140 Code Issues Pull requests Control and status register code generator toolchain asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model Updated May 23, 2025 Python
vyges / fast-fourier-transform-ip Star 0 Code Issues Pull requests Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency. asic fpga pipeline signal-processing rad verilog digital-signal-processing apb ip-core hardware-ip vyges vyges-ip ix-2 Updated Jul 23, 2025 Python