Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data
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Updated
Mar 5, 2026 - Python
Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data
Design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit Version 1.
⚡ A seamless integration of HuggingFace Transformers & Diffusers with RBLN SDK for efficient inference on RBLN NPUs.
KV260 integration lane for PCCX™ v002 LLM IP-core bring-up, validation, and board/runtime evidence.
PyTorch extension for Rebellions NPU
An out-of-tree vLLM plugin for Mobilint NPU runtime integration.
PCCX™ specification, documentation, and ecosystem coordination hub for open AI accelerator IP.
Bachelor's Final Year Project an FPGA-based FP16 CNN accelerator for real-time YOLOv8n object detection on Xilinx Zynq UltraScale+ (ZCU104). Features a reconfigurable multi-engine architecture with on-chip dynamic retiling, achieving scalable throughput for edge AI applications.
Tenstorrent backend plugin for vLLM.
Pytorch implementation of TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
NPU soft IP, designed for true parallel execution on the edge.
Rapid prototyping framework for deploying and evaluating ML models on hardware
Publish and pull precompiled tt-metal kernel caches over Hugging Face Hub for Tenstorrent accelerators
T1C — Open-Source AI Accelerator Architecture. Like RISC-V did for CPUs, T1C does for AI chips. Fully open source, MIT Licensed.
Quiet the fan on Tenstorrent Blackhole PCIe accelerators under Windows. Minimal KMDF driver that sends ARC ASIC_STATE0 on D0Entry.
An 8×8 systolic array AI accelerator implemented in SystemVerilog on Zynq UltraScale+ ZCU104, achieving 1.7 GOPS at 6 mW PL logic power (~283 GOPS/W efficiency) with full AXI-Stream PS-PL integration. Targets INT8 matrix multiplication for transformer inference acceleration, verified across behavioral, post-synthesis and implementation simulation.
A curated collection of resources, research papers, tools, hardware, and learning roadmaps for Physical AI, Embodied AI, Vision-Language-Action (VLA) models, World Models, edge AI, and intelligent robotics.
This project implements AXI-based matrix multiply accelerator.
SGLang backend plugin for IBM Spyre AIU inference
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