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pinmux.c
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#include "types.h"
#include "riscv.h"
#include "defs.h"
#include "memlayout.h"
#include "param.h"
#include "pinmux.h"
#define BIT(nr) (1UL << (nr))
#define GPIO_DOEN_OFFSET 0x00
#define GPIO_DOUT_OFFSET 0x40
#define GPIO_SIGIN_OFFSET 0x80
#define SYS_IOMUX_GPO_DOEN_CFG_SHIFT 0x8
#define SYS_IOMUX_GPO_DOEN_CFG_MASK 0x3F
#define SYS_IOMUX_GPO_DOUT_CFG_SHIFT 0x8
#define SYS_IOMUX_GPO_DOUT_CFG_MASK 0x7F
#define SYS_IOMUX_GPO_SIGIN_CFG_SHIFT 0x8
#define SYS_IOMUX_GPO_SIGIN_CFG_MASK 0x7F
#define SYS_IOMUX_GPO_SIGIN_CFG_OFFSET 0x2 // from GPIO2 to GPIO63 (GPIO0 and GPIO1 not available)
#define Reg(reg) ((volatile uint64 *)(SYS_IOMUX + reg))
static uint32 read32_aligned(uint64 addr) {
uint32 data;
addr = addr & ~0x3; // Align address
asm volatile ("lw %0, 0(%1)" : "=r"(data) : "r"(Reg(addr)));
return data;
}
static void write32_aligned(uint64 addr, uint32 data) {
addr = addr & ~0x3; // Align address
asm volatile ("sw %0, 0(%1)" : : "r"(data), "r"(Reg(addr)));
}
static void write8_aligned(uint64 addr, uint8 data) {
uint64 offset = addr & 0x3; // Get offset
uint32 current_value = read32_aligned(addr);
uint32 mask = 0xFF << (offset * 8);
uint32 new_value = (current_value & ~mask) | (data << (offset * 8));
write32_aligned(addr, new_value);
}
static uint8 read8_aligned(uint64 addr) {
uint64 offset = addr & 0x3; // Get offset
uint32 data = read32_aligned(addr);
return (data >> (offset * 8)) & 0xFF;
}
static void write_GPIO_conf(uint64 reg, uint8 mask, uint8 value) {
uint8 data = read8_aligned(reg);
data = (data & ~mask) | (value & mask);
write8_aligned(reg, data);
}
void set_pinmux_gpio_doen(uint8 gpio_num, uint8 signal) {
if (gpio_num > 63) {
printf("Invalid GPIO number: %d\n", gpio_num);
return;
}
if (signal > SYS_IOMUX_GPO_DOEN_CFG_MASK) {
printf("Invalid signal value: %d\n", signal);
return;
}
write_GPIO_conf(GPIO_DOEN_OFFSET + gpio_num,
SYS_IOMUX_GPO_DOEN_CFG_MASK,
signal);
}
void set_pinmux_gpio_dout(uint8 gpio_num, uint8 signal) {
if (gpio_num > 63) {
printf("Invalid GPIO number: %d\n", gpio_num);
return;
}
if (signal > SYS_IOMUX_GPO_DOUT_CFG_MASK) {
printf("Invalid signal value: %d\n", signal);
return;
}
write_GPIO_conf(GPIO_DOUT_OFFSET + gpio_num,
SYS_IOMUX_GPO_DOUT_CFG_MASK,
signal);
}
void set_pinmux_gpio_sigin(uint8 gpio_num, uint8 signal) {
if (gpio_num < 2 || gpio_num > 63) {
printf("Invalid GPIO number: %d\n", gpio_num);
return;
}
if (signal > SYS_IOMUX_GPO_SIGIN_CFG_MASK) {
printf("Invalid signal value: %d\n", signal);
return;
}
write_GPIO_conf(GPIO_SIGIN_OFFSET + signal,
SYS_IOMUX_GPO_SIGIN_CFG_MASK,
gpio_num + SYS_IOMUX_GPO_SIGIN_CFG_OFFSET);
}
void set_pin_func(uint8 pin, uint8 func) {
if (pin < 10 || pin > 63) {
printf("Invalid GPIO number, must be >= 10 and <= 63: %d\n", pin);
return;
}
// Calculate register offset and bit position
uint32 reg_offset = 0x29c + ((pin - 10) / 10) * 4;
uint32 bit_pos = ((pin - 10) % 10) * 3;
if (pin < 20) {
bit_pos += 2; // Account for reserved bits
}
uint32 val = read32_aligned(reg_offset);
val &= ~(0x7 << bit_pos);
val |= (func << bit_pos);
write32_aligned(reg_offset, val);
}
void pinmux_set_spi(uint8 spi_port, uint8 cs, uint8 miso, uint8 clk, uint8 mosi) {
// Only for VF2, can't do it in QEMU
#if defined(VF2)
uint32 clk_sig = 0, mosi_sig = 0, miso_sig = 0, cs_sig = 0;
switch (spi_port)
{
case 0:
clk_sig = GPO_SYS_IOMUX_U0_SSP_SPI_SSPCLKOUT;
mosi_sig = GPO_SYS_IOMUX_U0_SSP_SPI_SSPTXD;
miso_sig = GPI_SYS_IOMUX_U0_SSP_SPI_SSPRXD;
cs_sig = GPO_SYS_IOMUX_U0_SSP_SPI_SSPFSSOUT;
break;
case 1:
clk_sig = GPO_SYS_IOMUX_U1_SSP_SPI_SSPCLKOUT;
mosi_sig = GPO_SYS_IOMUX_U1_SSP_SPI_SSPTXD;
miso_sig = GPI_SYS_IOMUX_U1_SSP_SPI_SSPRXD;
cs_sig = GPO_SYS_IOMUX_U1_SSP_SPI_SSPFSSOUT;
break;
case 2:
clk_sig = GPO_SYS_IOMUX_U2_SSP_SPI_SSPCLKOUT;
mosi_sig = GPO_SYS_IOMUX_U2_SSP_SPI_SSPTXD;
miso_sig = GPI_SYS_IOMUX_U2_SSP_SPI_SSPRXD;
cs_sig = GPO_SYS_IOMUX_U2_SSP_SPI_SSPFSSOUT;
break;
case 3:
clk_sig = GPO_SYS_IOMUX_U3_SSP_SPI_SSPCLKOUT;
mosi_sig = GPO_SYS_IOMUX_U3_SSP_SPI_SSPTXD;
miso_sig = GPI_SYS_IOMUX_U3_SSP_SPI_SSPRXD;
cs_sig = GPO_SYS_IOMUX_U3_SSP_SPI_SSPFSSOUT;
break;
case 4:
clk_sig = GPO_SYS_IOMUX_U4_SSP_SPI_SSPCLKOUT;
mosi_sig = GPO_SYS_IOMUX_U4_SSP_SPI_SSPTXD;
miso_sig = GPI_SYS_IOMUX_U4_SSP_SPI_SSPRXD;
cs_sig = GPO_SYS_IOMUX_U4_SSP_SPI_SSPFSSOUT;
break;
case 5:
clk_sig = GPO_SYS_IOMUX_U5_SSP_SPI_SSPCLKOUT;
mosi_sig = GPO_SYS_IOMUX_U5_SSP_SPI_SSPTXD;
miso_sig = GPI_SYS_IOMUX_U5_SSP_SPI_SSPRXD;
cs_sig = GPO_SYS_IOMUX_U5_SSP_SPI_SSPFSSOUT;
break;
case 6:
clk_sig = GPO_SYS_IOMUX_U6_SSP_SPI_SSPCLKOUT;
mosi_sig = GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD;
miso_sig = GPI_SYS_IOMUX_U6_SSP_SPI_SSPRXD;
cs_sig = GPO_SYS_IOMUX_U6_SSP_SPI_SSPFSSOUT;
break;
default:
printf("Invalid SPI port\n");
break;
}
// Enable ouputs
set_pinmux_gpio_doen(cs, 0);
set_pinmux_gpio_doen(clk, 0);
set_pinmux_gpio_doen(mosi, 0);
// Enable inputs
set_pinmux_gpio_doen(miso, 1);
set_pinmux_gpio_dout(cs, cs_sig);
set_pinmux_gpio_dout(clk, clk_sig);
set_pinmux_gpio_dout(mosi, mosi_sig);
set_pinmux_gpio_sigin(miso, miso_sig);
#endif
}