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Fix the port to the x86 Architecture #4385

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Pull Request Overview

This pull request fixes the #4171:

  • removes the external dependency to the x86 crate
  • replaces the x86 structures using tock-registers
  • fixes some lints

Testing Strategy

This pull request was tested by @ioanaculic.

TODO or Help Wanted

Rebase and feeback.

I would like to get some feedback before I rebase this.

Documentation Updated

  • Updated the relevant files in /docs, or no updates are required.

Formatting

  • Ran make prepush.

bradjc
bradjc previously approved these changes Mar 26, 2025
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This is awesome!!

Note, I haven't reviewed any of the code, but the general directory structure looks good to me.

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I don't know what the right name is, but "pc" seems too generic. Is there something reasonable that is more specific we could call this crate?

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I don't know why this is marked outdated. It looks like this is still a relevant question.

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The intention of this chip crate is to provide drivers for peripherals found on what I'd call "legacy PC BIOS" platforms - Mostly older I/O port-based devices which are available in QEMU (and possibly still found on modern PC systems?) - but which are not strictly part of the ISA itself. Totally open to suggestions on what a better name could be, maybe pc_bios?

Might also be worth debating whether this is actually a "chip" crate, or perhaps the drivers belong in the board folder somewhere to be shared by other boards that fall into the "PC BIOS" category.

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My take on this is that the chips crate represents an SoC. In the case of x86, the SoC does not actually exist, but I mostly composed out of the procesor and the mainboard (chipset + default peripherals). I would suggest renaming it to x86_q35.

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What's in the chip crate does the things that chip crates do, so I think that is the right place.

It's fine to have two crates, maybe pc and q35, with q35 just re-exporting what is in pc. Then the board includes q35. The pc crate can contain a host of peripherals, and more specific chip crates include what is relevant.

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For now I would suggest to leave one single crate as we have only q35 supported and if another x86 chip is added we can do the split.

This is similar to how the STM chips where added.

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What is that crate called?

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stm32f4xx and nrf5x

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But what would it be called in this PR?

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I would suggest to name it x86_q35, as @alexandruradovici suggested.

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alevy commented Mar 26, 2025

@reynoldsbd et al, are you able to maybe take a look at this? In particular, you might have the ability to test functional correctness with a downstream with more functionality elsewhere.

In general, my sense is that this looks like what we would want upstream, and if it otherwise smells right (basically works and doesn't have soundness etc issues), we should merge and fix functional issues as they arise (potentially as downstream users find them when moving to this implementation).

Co-authored-by: Brad Campbell <bradjc5@gmail.com>
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This is awesome, thanks so much @ioanaculic for taking this closer to the finish line! :)

This all looks sensible on first glance. My team is doing some internal validation as well to make sure this all continues to work on our platforms. I'll follow up once we have some results to share. cc @alevy

One last topic: Apart from the x86 dependency, it's not immediately clear to me whether any of the other feedback or pending opens from the original PR have been addressed in this new PR. There was some good feedback over there and I'd hate for it to slip through the cracks. It'd also be nice to have the original PR description copied over to this one; I personally place high value on leaving a good trail in Git history, but I recognize that's not a top priority for everyone.

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We've discussed this briefly on the core call today.

@reynoldsbd It seems like this already includes all of the other changes which you made on the original PR in response to feedback, and is a strict superset of the commits of that PR.

Therefore, it seems easiest to reference back to #4171, perhaps take some of the original PR's description and feedback integrate it into this one, and finally push this new PR over the finish line.

One of our remaining concerns is around testing these changes, especially running userspace applications, and testing the memory protection implementation. One thing that could allow us to better test these changes is if you could provide a small dummy / test application (either in source or binary form), with instructions on how to load it?

This all looks sensible on first glance. My team is doing some internal validation as well to make sure this all continues to work on our platforms. I'll follow up once we have some results to share. cc @alevy

It's great to hear that you're testing these changes internally. We'd thus holding off on merging this for a couple more days, and can use that time to gather more reviews generally.

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bradjc commented Apr 2, 2025

We need to document how to get qemu. The getting started guide doesn't actually include those instructions.

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Good news, we confirmed this is all running smoothly on real silicon!

@HMiyaziwala has opened a PR in the libtock-rs repo to add support for x86. That should allow you to use one of the example apps for testing.

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We need to document how to get qemu. The getting started guide doesn't actually include those instructions.

Done.

@ioanaculic ioanaculic force-pushed the delete_x86_dependency branch from eaeeec8 to e5f144a Compare April 25, 2025 10:21
Comment on lines -63 to 65
TARGET := $(patsubst "%",%,$(TARGET_QUOTES))
TARGET := $(patsubst "%",%,$(TARGET_QUOTES))
TARGET := $(subst .json,,$(patsubst "%",%,$(TARGET_QUOTES)))
endif
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revert

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Apart from my and @bradjc's comments, I think this is good to go.

@@ -0,0 +1,2 @@
x86 Architecture Support Components
===================================
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This would be a good place to specify what's supported (e.g. that it's 32 bit) as well as any caveats or specific decisions (which features are used, any relationship to specific x86 variants, such as 486 vs 386 vs ...), perhaps specifically how segmentation vs. virtual memory are used in this implementation.

/// - 4 dwords for initial upcall arguments
/// - 1 dword for initial upcall return address (although this will be zero for init_fn)
/// - 4 dwords of scratch space for invoking memop syscalls
const MIN_APP_BRK: u32 = 9 * 4;
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I wonder if this should be 9 * core::mem::size_of::<usize>() instead of a hard-coded 4, so it would more likely not require changes for 64 bit as well in the future?

// - the pointers are properly aligned. This is guaranteed because the
// pointers are all offset multiples of 4 bytes from the stack
// pointer, which is guaranteed to be properly aligned after
// exception entry on Cortex-M. See
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on Cortex-M.

Oops...

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7 participants