Prototype i32x4.widen_i8x16_{s,u}

As proposed in WebAssembly/simd#395. Note that the other
instructions in the proposal have not been implemented in LLVM or in V8, so
there is no need to implement them in Binaryen right now either. This PR
introduces a new expression class for the new instructions because they uniquely
take an immediate argument identifying which portion of the input vector to
widen.

Author: tlively

scripts/gen-s-parser.py

@@ -522,6 +522,8 @@
     ("i32x4.trunc_sat_f64x2_zero_u",  "makeUnary(s, UnaryOp::TruncSatZeroUVecF64x2ToVecI32x4)"),
     ("f32x4.demote_f64x2_zero",       "makeUnary(s, UnaryOp::DemoteZeroVecF64x2ToVecF32x4)"),
     ("f64x2.promote_low_f32x4",       "makeUnary(s, UnaryOp::PromoteLowVecF32x4ToVecF64x2)"),
+    ("i32x4.widen_i8x16_s",           "makeSIMDWiden(s, SIMDWidenOp::WidenSVecI8x16ToVecI32x4)"),
+    ("i32x4.widen_i8x16_u",           "makeSIMDWiden(s, SIMDWidenOp::WidenUVecI8x16ToVecI32x4)"),
 
     # prefetch instructions
     ("prefetch.t",  "makePrefetch(s, PrefetchOp::PrefetchTemporal)"),

src/gen-s-parser.inc

@@ -1832,6 +1832,17 @@ switch (op[0]) {
                           default: goto parse_error;
                         }
                       }
+                      case 'i': {
+                        switch (op[18]) {
+                          case 's':
+                            if (strcmp(op, "i32x4.widen_i8x16_s") == 0) { return makeSIMDWiden(s, SIMDWidenOp::WidenSVecI8x16ToVecI32x4); }
+                            goto parse_error;
+                          case 'u':
+                            if (strcmp(op, "i32x4.widen_i8x16_u") == 0) { return makeSIMDWiden(s, SIMDWidenOp::WidenUVecI8x16ToVecI32x4); }
+                            goto parse_error;
+                          default: goto parse_error;
+                        }
+                      }
                       case 'l': {
                         switch (op[22]) {
                           case 's':

src/ir/ReFinalize.cpp

@@ -112,6 +112,7 @@ void ReFinalize::visitSIMDLoad(SIMDLoad* curr) { curr->finalize(); }
 void ReFinalize::visitSIMDLoadStoreLane(SIMDLoadStoreLane* curr) {
   curr->finalize();
 }
+void ReFinalize::visitSIMDWiden(SIMDWiden* curr) { curr->finalize(); }
 void ReFinalize::visitPrefetch(Prefetch* curr) { curr->finalize(); }
 void ReFinalize::visitMemoryInit(MemoryInit* curr) { curr->finalize(); }
 void ReFinalize::visitDataDrop(DataDrop* curr) { curr->finalize(); }

src/ir/cost.h

@@ -540,6 +540,7 @@ struct CostAnalyzer : public OverriddenVisitor<CostAnalyzer, Index> {
   Index visitSIMDShift(SIMDShift* curr) {
     return 1 + visit(curr->vec) + visit(curr->shift);
   }
+  Index visitSIMDWiden(SIMDWiden* curr) { return 1 + visit(curr->vec); }
   Index visitSIMDShuffle(SIMDShuffle* curr) {
     return 1 + visit(curr->left) + visit(curr->right);
   }

src/ir/effects.h

@@ -430,6 +430,7 @@ class EffectAnalyzer {
       }
       parent.implicitTrap = true;
     }
+    void visitSIMDWiden(SIMDWiden* curr) {}
     void visitPrefetch(Prefetch* curr) {
       // Do not reorder with respect to other memory ops
       parent.writesMemory = true;

src/passes/Print.cpp

@@ -671,6 +671,19 @@ struct PrintExpressionContents
     }
     o << " " << int(curr->index);
   }
+  void visitSIMDWiden(SIMDWiden* curr) {
+    prepareColor(o);
+    switch (curr->op) {
+      case WidenSVecI8x16ToVecI32x4:
+        o << "i32x4.widen_i8x16_s ";
+        break;
+      case WidenUVecI8x16ToVecI32x4:
+        o << "i32x4.widen_i8x16_u ";
+        break;
+    }
+    restoreNormalColor(o);
+    o << int(curr->index);
+  }
   void visitPrefetch(Prefetch* curr) {
     prepareColor(o);
     switch (curr->op) {
@@ -2303,6 +2316,13 @@ struct PrintSExpression : public OverriddenVisitor<PrintSExpression> {
     printFullLine(curr->vec);
     decIndent();
   }
+  void visitSIMDWiden(SIMDWiden* curr) {
+    o << '(';
+    PrintExpressionContents(currFunction, o).visit(curr);
+    incIndent();
+    printFullLine(curr->vec);
+    decIndent();
+  }
   void visitPrefetch(Prefetch* curr) {
     o << '(';
     PrintExpressionContents(currFunction, o).visit(curr);

src/wasm-binary.h

@@ -979,6 +979,9 @@ enum ASTNodes {
   F32x4DemoteZeroF64x2 = 0x57,
   F64x2PromoteLowF32x4 = 0x69,
 
+  I32x4WidenSI8x16 = 0x67,
+  I32x4WidenUI8x16 = 0x68,
+
   // prefetch opcodes
 
   PrefetchT = 0xc5,
@@ -1521,6 +1524,7 @@ class WasmBinaryBuilder {
   bool maybeVisitSIMDShift(Expression*& out, uint32_t code);
   bool maybeVisitSIMDLoad(Expression*& out, uint32_t code);
   bool maybeVisitSIMDLoadStoreLane(Expression*& out, uint32_t code);
+  bool maybeVisitSIMDWiden(Expression*& out, uint32_t code);
   bool maybeVisitPrefetch(Expression*& out, uint32_t code);
   bool maybeVisitMemoryInit(Expression*& out, uint32_t code);
   bool maybeVisitDataDrop(Expression*& out, uint32_t code);

src/wasm-delegations-fields.h

@@ -386,6 +386,14 @@ switch (DELEGATE_ID) {
     DELEGATE_END(SIMDLoadStoreLane);
     break;
   }
+  case Expression::Id::SIMDWidenId: {
+    DELEGATE_START(SIMDWiden);
+    DELEGATE_FIELD_CHILD(SIMDWiden, vec);
+    DELEGATE_FIELD_INT(SIMDWiden, op);
+    DELEGATE_FIELD_INT(SIMDWiden, index);
+    DELEGATE_END(SIMDWiden);
+    break;
+  }
   case Expression::Id::PrefetchId: {
     DELEGATE_START(Prefetch);
     DELEGATE_FIELD_CHILD(Prefetch, ptr);

src/wasm-delegations.h

@@ -40,6 +40,7 @@ DELEGATE(SIMDTernary);
 DELEGATE(SIMDShift);
 DELEGATE(SIMDLoad);
 DELEGATE(SIMDLoadStoreLane);
+DELEGATE(SIMDWiden);
 DELEGATE(Prefetch);
 DELEGATE(MemoryInit);
 DELEGATE(DataDrop);

src/wasm-interpreter.h

@@ -1132,6 +1132,7 @@ class ExpressionRunner : public OverriddenVisitor<SubType, Flow> {
     }
     WASM_UNREACHABLE("invalid op");
   }
+  Flow visitSIMDWiden(SIMDWiden* curr) { WASM_UNREACHABLE("unimp"); }
   Flow visitSelect(Select* curr) {
     NOTE_ENTER("Select");
     Flow ifTrue = visit(curr->ifTrue);